STPMC1 datasheet(61/77 Pages) STMICROELECTRONICS

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STPMC1

Theory of operation

Doc ID 15728 Rev 6

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the SCS status. If SCS is low, SCLNCL is the input of serial bit synchronization clock signal.

When SCS is high, SCLNLC determines idle state of the SPI.

SDATD: is the data pin. If SCS is low, the operation of SDATD is dependent on the status of

SYN pin. If SYN is high SDATD is the output of serial bit data (read mode) if SYN is low

SDATD is the input of serial bit data signal (write mode). If SCS is high SDATD is input of

idle signal.

Any of the pins above has an internal weak pull-up device of a nominal 15 A. This means

that when a pin is not forced by external signals, the state of the pin is logic high. A high

state of any of the input pins above is considered in an idle (not active) state.

For the SPI to operate correctly the STPMC1 must be correctly supplied as described in the

power supply section. Idle state of SPI module is recognized when the signals of pins SYN,

SCS, SCLNLC and SDATD are in a logic high state. Any SPI operations should start from

such an idle state. The exception to this rule is when the STPMC1 has been put into

standalone application mode. In this mode it is possible that the states of the pins SCLNLC,

SDATD and SYN are not high due to the states of the corresponding internal status bits.

When SCS is active (low), signal SDATD should change its state at the trailing edge of the

signal SCLNLC and signal SDATD should be stable at the next leading edge of signal

SCLNLC. The first valid bit of SDATD is always started with activation of signal SCLNLC.

9.21.1

Remote reset

The timing diagram of the operation is shown in remote reset request timing. The time step

can be as short as 30 ns.

The internal reset signal is called RRR. Unlike the POR, the RRR signal does not cause the

125 ms delayed restart of the digital module. This signal does not clear the mode signals.

Note:

All the time intervals must be longer than 30 ns.

t7 -> t8 is the reset time, this interval must be longer than 30 ns as well.

Figure 21.

Timing for providing remote reset request

SCS

SYN

SCLNLC

SDATD

SCS

SYN

SCLNLC

SDATD

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