STPMC1 datasheet(56/77 Pages) STMICROELECTRONICS

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Theory of operation

STPMC1

56/77

Doc ID 15728 Rev 6

Address

Name

N. of

bits

Description

IMPORTANT: The decimal value indicated in this column represents

the value of the configuration bits with MSB in bold.

7-BIT

Binary

DEC

0001000

ART

Reactive energy computation algorithm:

- ART=0: natural computation

- ART=1: artificial computation – not allowed if FUND =1

0001001

MSBF

Bit sequence output during record data reading selection:

- MSBF=0: msb first

- MSBF=1: lsb first

0001010

0001011

ABS

Negative power accumulation type:

- ABS=0: 3-phase Ferraris,

- ABS=1: absolute accumulation per phase

- ABS=2: Ferraris per phase,

- ABS=3: signed accumulation

0001100

0001101

LTCH

No-load condition threshold:

- LTCH=0: 0,00125 * FS,

- LTCH=1: 0,0025 * FS

- LTCH=2: 0,005 * FS

- LTCH=3: 0,010 * FS

0001110

0001111

KMOT

If APL=0 output selection for LED pin:

KMOT=0

KMOT=1

KMOT=2

KMOT=3

3-phase

R phase

S phase

T phase

If APL = 1, 2, 3 pulsed output divider:

If LVS=0,

KMOT=0

KMOT=1

KMOT=2

KMOT=3

P/64

P/128

P/32

P/256

The constants at LVS=0 is valid also for LED when APL=3

If LVS=1,

KMOT=0

KMOT=1

KMOT=2

KMOT=3

P/640

P/1280

P/320

P/2560

0010000

LVS

if APL = 0, 1 Selection of pulses(X) for LED:

- LVS=0: active power,

- LVS=1: reactive power.

if APL = 1, 2, 3 Type of stepper selection:

- LVS=0: 10 poles, 30ms, 5V stepper,

- LVS=1: 2 poles, 150ms, 3V stepper

0010001

0010010

0010011

SYS

Measurement system selection:

- SYS=0: 3-phase, 4-wire RSTN, 4-systxem RSTN (tamper)

- SYS=1: 3-phase, 4-wire RSTN, 3-system RST_

- SYS=2: 3-phase, 3-wire RST_, 3-system RST_ (tamper)

- SYS=3: 3-phase, 3-wire RST_, 2-system R_T_ (Aron)

- SYS=4: 2-phase, 3-wire _STN, 2-system _ST_ (America)

- SYS=5: 1-phase, 2-wire __TN, 2-system _ST_ (tamper coil:coil)

- SYS=6: 1-phase, 2-wire __TN, 2-system _ST_ (tamper coil:shunt)

- SYS=7: 1-phase, 2-wire __TN, 1-system __T_

0010100

SCLP

Polarity of SCLNLC idle state selection:

- SCLP=0: idle state SCLNLC=1,

- SCLP=1: idle state SCLNLC=0

Table 33.

Configuration bits map (continued)

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