STPMC1 datasheet(23/77 Pages) STMICROELECTRONICS

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STPMC1

Theory of operation

Doc ID 15728 Rev 6

23/77

The clock generator is responsible for two tasks.

The first is to retard the turn-on of some functional blocks after POR in order to help a

smooth start of external power supply circuitry by keeping off all major loads. For this

reason, all blocks of the digital part, except the SPI interface, are held in a reset state for 125

ms after a power on reset (see

Section 9.3).

The second task of the clock generator is to provide all necessary clocks for the digital part.

In this task, a MDIV and FR1 programming bits are used to inform the device about the

nominal frequency value from XTAL1 (fXTAL1).

Four nominal frequencies are possible through proper setting of the MDIV and FR1 bits (see

Table 10).

The internal master clock fMCLK is derived from fXTAL1 as shown in Table 10.

Through the HSA bit the frequency of the output pin CLK (fCLK), which provides the clock for

the STPMSx devices, can be derived as reported in

Table 11.

To properly work with STPMS2, the clock configurations in

Table 12 must be used.

Moreover, with STPMS2 companion chip the PM bit must always be set.

9.5

Zero crossing detection (signal

ZCR)

The STPMC1 has a zero crossing detection circuit on the voltage channel that can be used

to synchronize some utility equipment to zero crossing or max of line voltage events. This

circuit produces the internal signal

ZCR that has a falling edge every zero crossing of one of

the line voltages and a rising edge every peak (positive or negative) of one of the line

voltages.

Table 10.

Frequency settings through MDIV and FR1 (1)

4 MHz and 8 MHz clock are also supported. MDIV and FR1 have to be set as for 4.194 MHz and 8.192

MHz respectively.

fXTAL1

MDIV (1 bit)

FR1 (1 bit)

fMCLK

4.194 MHz

8.389 MHz

4.915 MHz

9.830 MHz

8.192 MHz

9.830 MHz

Table 11.

CLK pin frequency settings through HSA

HSA (1 bit)

fCLK STPMC1

0fXTAL1 / 4

1fXTAL1 / 2

Table 12.

STPMC1 configuration for STPMS2

MDIV (1 bit)

HSA (1 bit)

fCLK

fXTAL1 / 4

fXTAL1 / 2

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