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M24LR04E-R 数据表(PDF) 125 Page - STMicroelectronics

部件名 M24LR04E-R
功能描述  4-Kbit EEPROM with password protection, dual interface & energy harvesting: 400 kHz I²C bus & ISO 15693 RF protocol at 13.56 MHz
PDF  142 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M24LR04E-R 数据表(HTML) 125 Page - STMicroelectronics

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M24LR04E-R
I2C DC and AC parameters
Doc ID 022208 Rev 5
125/142
Table 122.
I2C AC characteristics
Test conditions specified in Table 118
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock frequency
25
400
kHz
tCHCL
tHIGH
Clock pulse width high
0.6
20000(1)
1.
tCHCL timeout
µs
tCLCH
tLOW
Clock pulse width low
1.3
20000(2)
2.
tCLCH timeout
µs
tSTART_OU
T
I²C timeout on Start condition
40
ms
tXH1XH2
(3)
3.
Values recommended by the I²C-bus Fast-Mode specification.
tR
Input signal rise time
20
300
ns
tXL1XL2
(3)
tF
Input signal fall time
20
300
ns
tDL1DL2
tF
SDA (out) fall time
20
100
ns
tDXCX
tSU:DAT Data in set up time
100
ns
tCLDX
tHD:DAT Data in hold time
0
ns
tCLQX
tDH
Data out hold time
100
ns
tCLQV
(4)(5)
4.
To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5.
tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a
compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus
× Cbus time constant is less than 500 ns (as specified in Figure 3).
tAA
Clock low to next data valid (access time)
100
900
ns
tCHDX
(6)
6.
For a reStart condition, or following a write cycle.
tSU:STA Start condition set up time
600
ns
tDLCL
tHD:STA Start condition hold time
0.6
35000(7)
7.
tDLCL timeout
µs
tCHDH
tSU:STO Stop condition set up time
600
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
ns
tW
I²C write time
5
ms



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