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AD1816AJS 数据表(PDF) 36 Page - Analog Devices |
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AD1816AJS 数据表(HTML) 36 Page - Analog Devices |
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36 / 52 page  AD1816A –36– REV. A [33] DSP CONFIGURATION DEFAULT = [0x0000] 7654321076543210 DS1 DS0 DIT RES ADR I1T I0T CPI PBI FMI I1I I0I DFS [2:0] DFS [2:0] DSP Frame Sync Source. Sets the DSP Port Frame Sync according to the following source. 000—Maximum Frame Rate 001—I 2S(0) Sample Rate 010—I 2S(1) Sample Rate 011—Music Synthesizer Sample Rate 100—Sound System Playback Sample Rate 101—Sound System Capture Sample Rate 111—Reserved I0I I 2S(0) Data Intercept. 0 = Disable, 1 = Intercept I2S(0) Data Enabled. I1I I 2S(1) Data Intercept. 0 = Disable, 1 = Intercept I2S(1) Data Enabled. FMI FM Music Synthesizer Data Intercept. 0 = Disable, 1 = Intercept FM Music Data Enabled. PBI Playback Data Intercept. 0 = Disable, 1 = Intercept Playback Data Enabled. CPI Capture Data Intercept. 0 = Disable, 1 = Intercept Capture Data Enabled. I0T I 2S(0) Takeover Data. 0 = Disable, 1 = Enabled. I1T I 2S(1) Takeover Data. 0 = Disable, 1 = Enabled. ADR Audio Resync. Writing “1” causes all FIFOs in the DSP port to be re-initialized. DIT DSP Interrupt. A write to this bit causes an ISA interrupt if DIE is asserted. DS0 DSP Mailbox 0 Status. 0 = last access indicates read, 1 = last access indicates write. DS1 DSP Mailbox 1 Status. 0 = last access indicates read, 1 = last access indicates write. [34] FM SAMPLE RATE DEFAULT = [0x5622] 7654321076543210 FMSR [15:8] FMSR [7:0] FMSR [15:0] F Music Sample Rate register. The sample rate can be programmed from 4 kHz to 27.6 kHz in 1 hertz increments. [35] I 2S(1) SAMPLE RATE DEFAULT = [0xAC44] 7654321076543210 S1SR [15:8] S1SR [7:0] S1SR [15:0] I 2S(1) Sample Rate register. The sample rate can be programmed from 4 kHz to 55.2 kHz in 1 hertz increments. Programming this register has no effect unless I 2SF1 [1:0] is enabled. [36] I 2 S(0) SAMPLE RATE DEFAULT = [0xAC44] 7654321076543210 S0SR [15:8] S0SR [7:0] S0SR [15:0] I 2S(0) Sample Rate register. The sample rate can be programmed from 4 kHz to 55.2 kHz in 1 hertz increments. Programing this register has no effect unless I 2SF0 [1:0] is enabled. [37] RESERVED DEFAULT = [0x0000] 7654321076543210 RES RES [38] PROGRAMMABLE CLOCK RATE DEFAULT = [0xAC44] 7654321076543210 PCR [15:8] PCR [7:0] PCR [15:0] Programmable Clock Rate register. The clock rate can be programmed from 25 kHz to 50 kHz in 1 hertz increments. This register is only valid when the COF bits in SS [32] are set for the multiplier factor. PCLKO = 256 × PCR/2COF. See SS [32] for determining the value of COF. [39] 3D Phat Stereo Control and PHONE_OUT Attenuation DEFAULT = [0x8000] 7654321076543210 3DDM RES 3DD [3:0] RES POM RES POA [4:0] POA [4:0] PHONE-OUT Attenuation. The LSB represents –1.5 dB, 0000 = 0 dB and the range is 0 dB to –46.5 dB. |
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