AD1816AJS datasheet(25/52 Pages) AD

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AD1816A

–25–

REV. A

[Base+4]

PIO Debug

76543210

RES

PUR

COR

ORR[1:0]

ORL[1:0]

RESET = [0x00]

All bits in this register are sticky until any write that clears all bits to 0.

ORL/ORR (RO)

Overrange Left/Right detect. These bits record the largest output magnitude on the ADC right and left

[1:0]

channels and are cleared to 00 after any write to this register. The peak amplitude as recorded by these bits is

“sticky,” i.e., the largest output magnitude recorded by these bits will persist until these bits are explicitly

cleared. They are also cleared by powering down the chip.

ORL/ORR

Over/Under Range Detection

Less than –1 dB Underrange

Between –1 dB and 0 dB Underrange

Between 0 dB and 1 dB Overrange

Greater than 1 dB Overrange

COR

(RO)

Capture Over Run. The codec sets (1) this bit when capture data is not read within one sample period after the

capture FIFO fills. When COR is set, the FIFO is full and the codec discards any new data generated. The

codec clears this bit immediately after a 4 byte capture sample is read.

PUR

(RO)

Playback Under Run. The codec sets (1) this bit when playback data is not written within one sample period af-

ter the playback FIFO empties. The codec clears (0) this bit immediately after a 4 byte playback sample is writ-

ten. When PUR is set, the playback channel has “run out” of data and either plays back a midscale value or

repeats the last sample.

[Base+5]

PIO Status

76543210

PFH

PDR

PLR

PUL

CFH

CDR

CLR

CUL

RESET = [0x00]

CUL

(RO)

Capture Upper/Lower Sample. This bit indicates whether the PIO capture data ready is for the upper

or lower byte of the channel.

Lower byte ready

Upper byte ready or any 8-bit mode

CLR

(RO)

Capture Left/Right Sample. This bit indicates whether the PIO capture data waiting is for the left channel ADC

or the right channel ADC.

Right channel

Left channel or mono

CDR

(RO)

Capture Data Ready. The PIO Capture Data register contains data ready for reading by the host. This bit should be

used only when direct programmed I/O data transfers are desired (FIFO has at least 4 bytes before full).

ADC is stale. Do not reread the information

ADC data is fresh. Ready for next host data read

CFH

(RO)

Capture FIFO Half Full. (FIFO has at least 32 bytes before full.)

PUL

(RO)

Playback Upper/Lower Sample. This bit indicates whether the PIO playback data needed is for the upper or

lower byte of the channel.

Lower byte needed

Upper byte needed or any 8-bit mode

PLR

(RO)

Playback Left/Right Sample. This bit indicates whether the PIO playback data needed is or the left channel

DAC or the right channel DAC.

Right channel needed

Left channel or mono

PDR

(RO)

Playback Data Ready. The PIO Playback data register is ready for more data. This bit should only be used

when direct programmed I/O data transfers are desired (FIFO can take at least 4 bytes).

DAC data is still valid. Do not overwrite

DAC data is stale. Ready for next host data write value

PFH

(RO)

Playback FIFO Half Empty. FIFO can take at least 32 bytes, eight groups of 4 bytes.

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