AD1816AJS datasheet(33/52 Pages) AD

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AD1816A

–33–

REV. A

RS1M

Right I

2S(1) Mute. 0 = Unmuted, 1 = Muted.

LS1A [5:0]

Left I

2S(1) Attenuation register. The LSB represents –1.5 dB, 000000 = 0 dB and the range is 0 dB to –94.5 dB.

LS1M

Left I

2S(1) Mute. 0 = Unmuted, 1 = Muted.

[07] I

2S(0) ATTENUATION

DEFAULT = [0x8080]

7654321076543210

LS0M

RES

LS0A [5:0]

RS0M

RES

RS0A [5:0]

Right I

2S(0) Attenuation register. The LSB represents –1.5 dB, 000000 = 0 dB and the range is 0 dB to –94.5 dB.

RS0M

Right I

2S(0) Mute. 0 = Unmuted, 1 = Muted.

LS0A [5:0]

Left I

2S(0) Attenuation register. The LSB represents –1.5 dB, 000000 = 0 dB and the range is 0 dB to –94.5 dB.

LS0M

Left I

2S(0) Mute. 0 = Unmuted, 1 = Muted.

[08] PLAYBACK BASE COUNT

DEFAULT = [0x0000]

7654321076543210

PBC [15:8]

PBC [7:0]

PBC [15:0]

Playback Base Count. This register is for loading the Playback DMA Count. Writing a value to this register also

loads the same data into the Playback Current Count register. You must load this register when Playback Enable

(PEN) is deasserted. When PEN is asserted, the Playback Current Count decrements once for every four bytes

transferred via a DMA cycle. The next transfer, after zero is reached in the Playback Current Count, will generate

an interrupt and reload the Playback Current Count with the value in the Playback Base Count. The Playback Base

Count should always be programmed to Number Bytes divided by four, minus one ((Number Bytes/4) –1). The

circular software DMA buffer must be divisible by four to ensure proper operation.

[09] PLAYBACK CURRENT COUNT

DEFAULT = [0x0000]

7654321076543210

PCC [15:8]

PCC [7:0]

PCC [15:0]

Playback Current Count register. Contains the current Playback DMA Count. Reads and Writes must be done

when PEN is deasserted.

[10] CAPTURE BASE COUNT

DEFAULT = [0x0000]

7654321076543210

CBC [15:8]

CBC [7:0]

CBC [15:0]

Capture Base Count. This register is for loading the Capture DMA Count. Writing a value to this register also

loads the same data into the Capture Current Count register. Loading must be done when Capture Enable (CEN)

is deasserted. When CEN is asserted, the Capture Current Count decrements once for every four bytes transferred

via a DMA cycle. The next transfer, after zero is reached in the Capture Current Count, will generate an interrupt

and reload the Capture Current Count with the value in the Capture Base Count. The Capture Base Count should

always be programmed to Number Bytes divided by four, minus one ((Number Bytes/4) –1). The circular software

DMA buffer must be divisible by four to ensure proper operation.

[11] CAPTURE CURRENT COUNT

DEFAULT = [0x0000]

7654321076543210

CCC [15:8]

CCC [7:0]

CCC [15:0]

Capture Current Count register. Contains the current Capture DMA Count. Reading and Writing must be done

when CEN is deasserted.

[12] TIMER BASE COUNT

DEFAULT = [0x0000]

7654321076543210

TBC [15:8]

TBC [7:0]

TBC [15:0]

Timer Base Count. Writing a value to this register loads data into the Timer Current Count register. Loading must

be done when Timer Enable (TE) is deasserted. When TE is asserted, the Timer Current Count register decre-

ments once for every specified time period. The time period (10

µs or 100 ms) is programmed via the PTB bit in

SS [44]. When TE is asserted, the Timer Current Count decrements once every time period. The next count, after zero

is reached in the Timer Current Count register, will generate an interrupt and reload the Timer Current Count register

with the value in the Timer Base Count register.

AD1816AJS 数据表(PDF) 33 Page - Analog Devices

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AD1816AJS 数据表(PDF) 33 Page - Analog Devices

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