AD1816A

–37–

REV. A

POM

PHONE-OUT Mute. 0 = Unmuted, 1 = Muted.

3DD [3:0]

3D Depth Phat Stereo Enhancement Control. The LSB represents 6 2/3% phase expansion, 0000 = 0% and

the range is 0% to 100%.

3DDM

3D Depth Mute. Writing a “1” to this bit has the same affect as writing 0s to 3DD [3:0] bits, and causes

the Phat 3D Stereo Enhancement to be turned off. 0 = Phat Stereo is on, 1 = Phat Stereo is off.

[40] RESERVED

DEFAULT = [0x0000]

7654321076543210

RES

RES

[41] HARDWARE VOLUME BUTTON MODIFIER

DEFAULT = [0xXX1B]

7654321076543210

RES

VMU

VUP

VDN

BM [4:0]

BM [4:0]

Button Modifier

VDM

Volume Down

VUP

Volume Up

VMU

Volume Mute

This register contains a Master Volume attenuation offset, which can be incremented or decremented via the Hardware Volume

Pins. This register is summed with the Master Volume attenuation to produce the actual Master Volume DAC attenuation. A mo-

mentary grounding of greater than 50 ms on the

VOL_UP pin will cause a decrement (decrease in Attenuation) in this register.

Holding the pin LO for greater than 200 ms will cause an auto-decrement every 200 ms. This is also true for a momentary ground-

ing of the

VOL_DN pin. A momentary grounding of both the VOL_UP and VOL_DN causes a mute and no increment or decre-

ment to occur.

When Muted, an unmute is possible by a momentary grounding of both the

VOL_UP and VOL_DN pins together, a momen-

tary grounding of

VOL_UP (this also causes a volume increase), a momentary grounding of VOL_DN (this also causes a volume

decrease) or a write of “0” to the VI bit in SS [BASE+1].

[42] DSP MAILBOX 0

DEFAULT = [0x0000]

7654321076543210

MB0R [15:8]

MB0R [7:0]

MB0R [15:0]

This register is used to send data and control information to and from the DSP.

[43] DSP MAILBOX 1

DEFAULT = [0x0000]

7654321076543210

MB1R [15:8]

MB1R [7:0]

MB1R [15:0]

This register is used to send data and control information to and from the DSP.

[44] POWERDOWN AND TIMER CONTROL

DEFAULT = [0x0000]

7654321076543210

CPD

RES

PIW

PIR

PAA

PDA

PDP

PTB

3D

PD3D GPSP

RES

DM

RES

The AD1816A supports a timeout mechanism used in conjunction with the Timer Base Count and Timer Current Count registers

to generate a power-down interrupt. This interrupt allows software to power down the entire chip by setting the CPD bit. This

power-down control feature lets users program a time interval from 1 ms to approximately 1.8 hours in 1 ms increments. Five

power-down count reload enable bits are used to reload the Timer Current Count from the Timer Base Count when activity is

seen on that particular channel.

Programming Example: Generate Interrupt if No ISA Reads or Writes occur within 15 Minutes.

1) Write [SSBASE+0] with 0x0C ; Write Indirect address for TIMER BASE COUNT “register 12”

2) Write [SSBASE+2] with 0x28 ; Write TIMER BASE COUNT with (15 min

× 60 sec/min × 100 ms) = 0x2328; Note: PTB = 1,

timer decrements every 100 ms

3) Write [SSBASE+3] with 0x23 ; Write High byte of TIMER BASE COUNT

4) Write [SSBASE+0] with 0x2C ; Write Indirect address for POWER-DOWN and TIMER CONTROL register

5) Write [SSBASE+2] with 0x00 ; Write Low byte of POWER-DOWN and TIMER CONTROL register

6) Write [SSBASE+3] with 0x31 ; Set Enable bits for PIW and PIR

7) Write [SSBASE+0] with 0x01 ; Write Indirect address for INTERRUPT CONFIG register

8) Write [SSBASE+2] with 0x82 ; Set the TE (Timer Enable) bit

9) Write [SSBASE+3] with 0x20 ; Set the TIE (Timer Interrupt Enable) bit