AD1816A

–21–

REV. A

Figure 14 illustrates the flexibility of the DSP Serial Port interface. This port can monitor or intercept any of the digital streams man-

aged by the AD1816A. Any ADC or DAC data stream can be intercepted by the port, shipped to an external DSP or ASIC manipu-

lated, and returned to any DAC summing path or to the ADC.

PLUG AND PLAY

ISA BUS

PARALLEL

INTERFACE

AUDIO

PGA

AUDIO/

MODEM

SERIAL PORT INTERFACE

MUSIC

SYNTHESIZER

Σ

A

M

A

M

A

M

A

M

FORMAT

FIFO

FORMAT

FIFO

Figure 14. DSP Serial Port

ISA INTERFACE

AD1816A Chip Registers

Table II, Chip Register Diagram, details the AD1816A direct register set available from the ISA Bus. Prior to any accesses by the

host, the PC I/O addressable ports must be configured using the Plug and Play Resources.

Table II. Chip Register Diagram

Register Type-Register Name

Register PC I/O Address

Plug and Play

ADDRESS

0x279

WRITE_DATA

0xA79

READ_DATA

Relocatable in Range 0x203 – 0x3FF

Sound System Codec

CODEC REGISTERS

0x(SS Base+0 – SS Base+15)

Relocatable in Range 0x100 – 0x3FF

See Table V

SoundBlaster Pro

Music0: Address (w), Status (r)

(SB Base) Relocatable in Range 0x100 – 0x3F0

Music0: Data (w)

(SB Base+1)

Music1: Address (w)

(SB Base+2)

Music1: Data (w)

(SB Base+3)

Mixer Address (w)

(SB Base+4)

Mixer Data (w)

(SB Base+5)

Reset (w)

(SB Base+6 or 7)

Music0: Address (w)

(SB Base+8)

Music0: Data (w)

(SB Base+9)

Input Data (r)

(SB Base+A or +B)

Status (r), Output Data (w)

(SB Base+C or +D)

Status (r)

(SB Base+E or +F)