AD1816A

–46–

REV. A

Table XIV. AD1816A Pin Muxing

PQFP

TQFP

Pin Function

I/O

Flags Required

199

I

I

I

VOL_UP

II

2

100

I

I

I

VOL_DN

II

31

I

I

I

GND

I

I

68

66

XCTL0/PCLKO

O

RSTB_EN

PNPRST

O

RSTB_EN

69

67

XCTL1/RING

O (1)

XTRA_EN + XTRA_CS

LD_SEL1

O

XTRA_EN * XTRA_CS

75

73

IRQ(15)

O (2)

IRQSEL15_11

IRQ(11)

O (2)

IRQSEL15_11

76

74

IRQ(11)

O (2)

IRQSEL4_9_11

IRQ(9)

O (2)

IRQSEL4_9_11* MODEM_EN

IRQ(4)

O (2)

IRQSEL4_9_11* MODEM_EN

77

75

IRQ(10)

O (2)

IRQSEL4_10

IRQ(4)

O (2)

IRQSEL4_10

78

76

IRQ(9)

O (2)

IRQSEL9_14

IRQ(14)

O (2)

IRQSEL9_14

81

79

I

I

MODEM_EN * SUPER_EN * IRQ_EN

IRQ(3)

O (2)

(MODEM_EN + SUPER_EN + IRQ_EN) *

IRQSEL3_9

IRQ(9)

O (2)

(MODEM_EN + SUPER_EN + IRQ_EN) * IRQSEL3_9

82

80

I

I

MODEM_EN

MDM_IRQ

I

MODEM_EN

83

81

I

I

MODEM_EN * SUPER_EN * IRQ_EN

MDM_SEL

O (4)

MODEM_EN *

SUPER_EN

IRQ(12)

O (2)

(

MODEM_EN + SUPER_EN) * IRQ_EN * IRQSEL12_13

IRQ(13)

O (2)

(

MODEM_EN + SUPER_EN) * IRQ_EN * IRQSEL12_13

97

95

SPORT_SCLK

O

XTRA_EN * XTRA_HV

LD_SEL0

O

XTRA_EN

No Connect

O

XTRA_EN * XTRA_HV

98

96

SPORT_SDFS

O (3)

XTRA_EN * XTRA_HV

LD_DRQ

I

XTRA_EN *

XTRA_HV

VOL_UP

I

XTRA_HV

99

97

SPORT_SDO

O (3)

XTRA_EN * XTRA_HV

LD_DACK

O (3)

XTRA_EN *

XTRA_HV

VOL_DN

I

(XTRA_EN + XTRA_CS) * XTRA_HV

GND

I

XTRA_EN * XTRA_HV * XTRA_CS

100

98

SPORT_SDI

I

XTRA_EN * XTRA_HV

LD_IRQ

I

XTRA_EN

VOL_DN

I

XTRA_EN * XTRA_HV * XTRA_CS

GND

I

XTRA_EN * XTRA_HV * XTRA_CS

(1) Open-drain driver with internal weak pull-up.

(2) PC_IRQ pins are three-stated if not assigned to a logical device.

(3) A pull-up or pull-down resistor may be required if EEPROM is used, because this pin is three-stated while EEPROM is read.

(4) An internal pull-up holds this pin deasserted until the EEPROM is read.

NOTE

The direction of some pins (input vs. output) depends on the flags. In order to prevent conflicts on pins that may be both inputs and

outputs, the AD1816 and AD1816A disable the output drivers for those pins while the flags are being read from the EEPROM, and

keep them disabled if the EEPROM data is invalid.