AD1816AJS datasheet(31/52 Pages) AD

31 / 52 page

AD1816A

–31–

REV. A

Table VIII. Sound System Indirect Registers

(High Byte)

(Low Byte)

ADDRESS

7654321076543210

00 (0x00)

RES

LBTD [7:0]

01 (0x01)

PIE

CIE

TIE

VIE

DIE

RIE

JIE

SIE

XC1

XC0

02 (0x02)

VPSR [15.8]

VPSR [7:0]

03 (0x03)

VCSR [15:8]

VCSR [7:0]

04 (0x04)

LVM

RES

LVA [5:0]

RVM

RES

RVA [5:0]

05 (0x05)

LFMM

RES

LFMA [5:0]

RFMM

RES

RFMA [5:0]

06 (0x06)

LS1M

RES

LS1A [5:0]

RS1M

RES

RS1A [5:0]

07 (0x07)

LS0M

RES

LS0A [5:0]

RS0M

RES

RS0A [5:0]

08 (0x08)

PBC [15:8]

PBC [7:0]

09 (0x09)

PCC [15:8]

PCC [7:0]

10 (0x0A)

CBC [15:8]

CBC [7:0]

11 (0x0B)

CCC [15:8]

CCC [7:0]

12 (0x0C)

TBC [15:8]

TBC [7:0]

13 (0x0D)

TCC [15:8]

TCC [7:0]

14 (0x0E)

LMVM

RES

LMVA [4:0]

RMVM

RES

RMVA [4:0]

15 (0x0F)

LCDM

RES

LCDA [4:0]

RCDM

RES

RCDA [4:0]

16 (0x10)

LSYM

RES

LSYA [4:0]

RSYM

RES

RSYA [4:0]

17 (0x11)

LVDM

RES

LVDA [4:0]

RVDM

RES

RVDA [4:0]

18 (0x12)

LLM

RES

LLA [4:0]

RLM

RES

RLA [4:0]

19 (0x13)

MCM

M20

RES

MCA [4:0]

PIM

RES

PIA [3:0]

RES

20 (0x14)

LAGC

LAS [2:0]

LAG [3:0]

RAGC

RAS [2:0]

RAG [3:0]

32 (0x20)

WSE

CDE

RES

CNP

RES

COF [3:0]

I2SF1 [1:0]

I2SF0 [1:0]

33 (0x21)

DS1

DS0

DIT

RES

ADR

I1T

I0T

CPI

PBI

FMI

I1I

I01

DFS [2:0]

34 (0x22)

FSMR [15:8]

FMSR [7:0]

35 (0x23)

S1SR [15:8]

S1SR [7:0]

36 (0x24)

S0SR [15:8]

S0SR [7:0]

37 (0x25)

RES

38 (0x26)

PCR [15:8]

PCR [7:0]

39 (0x27)

3DDM

RES

3DD [3:0]

RES

POM

RES

POA [4:0]

40 (0x28)

RES

41 (0x29 )

RES

VMU

VUP

VDN

BM [4:0]

42 (0x2A)

MB0R [15:8]

MB0R [7:0]

43 (0x2B)

MB1R [15:8]

MB1R [7:0]

44 (0x2C)

CPD

RES

PIW

PIR

PAA

PDA

PDP

PTB

PD3D

GPSP

RES

45 (0x2D)

VER [15:8]

VER [7:0]

46 (0x2E)

RES

[00] INDIRECT LOW BYTE TMP

DEFAULT = [0xXX]

7654321076543210

RES

LBTD [7:0]

LBTD [7:0] Low Byte Temporary Data holding latch for register pair writes;

Written on any write to [SSBase + 2],

Read from [SSBase + 2] when the indirect address is 0x00.

[01] INTERRUPT ENABLE AND EXTERNAL CONTROL

DEFAULT = [0x0102]

7654321076

543210

PIE

CIE

TIE

VIE

DIE

RIE

JIE

SIE

RES

XC1

XC0

External Control 0. The state of this bit is reflected on the XCTL0 pin. This pin is also muxed with

PCLKO. COF must be greater than 0x1011 for PCLKO to be disabled, see SS [32].

XC1

External Control 1. The state of this bit is reflected on the XCTL1 pin. XCTL1 may also be used for

Ring-In Interrupt. Open drain output, contains internal pull-up ~ 0.5 mA.

Timer Enable Bit.

SIE

SoundBlaster Interrupt Enable; This bit must be set to enable Current Count Timer.

SoundBlaster Interrupt disabled

SoundBlaster Interrupt enabled

JIE

Joystick Interrupt Enable;

Joystick Interrupt disabled

Joystick Interrupt enabled

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