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AD1816AJS 数据表(PDF) 13 Page - Analog Devices |
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AD1816AJS 数据表(HTML) 13 Page - Analog Devices |
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13 / 52 page ![]() AD1816A –13– REV. A Muxed Serial Ports (8 mA Drivers) Pin Name PQFP TQFP I/O Description I 2S(0)_BCLK* 3 1 I I 2S (0) Bit Clock. I2S(0)_LRCLK* 2 100 I I2S (0) Left/Right Clock. I 2S(0)_DATA* 1 99 I I 2S (0) Serial Data Input. I 2S(1)_BCLK* 82 80 I I 2S (1) Bit Clock. I2S(1)_LRCLK* 83 81 I I2S (1) Left/Right Clock. I 2S(1)_DATA* 81 79 I I 2S (1) Serial Data Input. SPORT_SDI* 100 98 I Serial Port Digital Serial Input. SPORT_SCLK* 97 95 O Serial Port Serial Clock. SPORT_SDFS* 98 96 O Serial Port Serial Data Frame Synchronization. SPORT_SDO* 99 97 O Serial Port Serial Data Output. Miscellaneous Analog Pins Pin Name PQFP TQFP I/O Description VREF_X 36 34 O Voltage Reference. Nominal 2.25 volt reference available for dc-coupling and level-shifting. VREF_X should not be used to sink or source signal current. VREF_X should be bypassed with 10 µF and 0.1 µF parallel capacitors. VREF 35 33 I Voltage Reference Filter. Voltage reference filter point for external bypassing only. VREF should be bypassed with 10 µF and 0.1 µF parallel capacitors. L_FILT 38 36 I Left Channel Filter. Requires a 1.0 µF to analog ground for proper operation. R_FILT 37 35 I Right Channel Filter. Requires a 1.0 µF to analog ground for proper operation. L_AAFILT 40 38 I Left Channel Antialias Filter. This pin requires a 560 pF NPO capacitor to analog ground for proper operation. R_AAFILT 39 37 I Right Channel Antialias Filter. This pin requires a 560 pF NPO capacitor to analog ground for proper operation. Crystal Pin Pin Name PQFP TQFP I/O Description XTALO 64 62 O 33 MHz Crystal Output. If no Crystal is present leave XTALO unconnected. XTALI 63 61 I 33 MHz Clock. When using a crystal as a clock source, the crystal should be connected between the XTALI and XTALO pins. Clock input may be driven into XTALI in place of a crystal. When using an external clock, VIH must be 2.4 V rather than the VIH of 2.0 V specified for all other digital inputs. External Logical Devices Pin Name PQFP TQFP I/O Description LD_IRQ* 100 98 I Logical Device IRQ. LD_DACK* 99 97 O Logical Device DACK. LD_DRQ* 98 96 I Logical Device DRQ. LD_SEL* 97 95 O Logical Device Select. MDM_SEL* 83 81 O Modem Chip Set Select. MDM_IRQ* 82 82 I Modem Chip Set IRQ. LD_SEL1* 69 67 O Logical Device (1) Select. PNPRST* 68 66 O Plug and Play Reset. |
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