AD9852SLASHPCB datasheet(34/42 Pages) AD

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AD9852

–34–

REV. 0

Attach power wires to connector labeled “TB1” using the screw-

down terminals. This is a plastic connector that press-ﬁts over a

4-pin header soldered to the board. Table IX below shows con-

nections to each pin. DUT = “device under test.”

Table IX. Power Requirements for DUT Pins

AVDD 3.3 V

DVDD 3.3 V

VCC 3.3 V

Ground

for All DUT

for All Other

—for All

Analog Pins

Digital Pins

Devices

Attach REFCLK

There are three possibilities to choose from:

1. On-Board (But Optional) Crystal Clock Oscillator, Y1.

Insert an appropriate 3.3 V CMOS clock oscillator. See that

the shorting jumper at W5 is located on Pins 1 and 2 (the left

two pins). This routes the single-ended oscillator output to a

very high speed “Differential Receiver” (the MC100LVEL16),

where the signal is transformed to a differential PECL output.

To route the differential output signals to AD9852, two more

switches must be conﬁgured. W9 must have a shorting jumper

on Pins 2 and 3 (the right two pins). To engage the differen-

tial clocking mode of the AD9852 W3, Pins 2 and 3 (the right

two pins) must be connected with a shorting jumper.

2. External Differential Clock Input, J5.

This is actually just another single-ended input that will be

routed to the MC100LVEL16 for conversion to differential

PECL output. This is accomplished by attaching a 2 V p-p

clock or sine wave source to J5. Note that this is a 50

Ω

impedance point set by R8. The input signal will be ac-

coupled and then biased to the center switching threshold

of the MC100LVEL16. Position the shorting jumper of W5

to Pins 2 and 3 (the right two pins) to route the signal at J5

to the differential receiver IC. To route the differential output

signals to AD9852, two more switches must be conﬁgured.

W9 must have a shorting jumper on Pins 2 and 3 (the right

two pins). To engage the differential clocking mode of the

AD9852 W3, Pins 2 and 3 (the right two pins) must be

connected with a shorting jumper.

3. External Single-Ended Clock Input, J7.

This mode bypasses the MC100LVEL16 and directly drives

the AD9852 with your reference clock. Attach a 50

Ω, 2 V p-p

sine source that is dc offset to 1.65 V, or a 50

Ω CMOS-level

clock source to J7. Remove the shorting jumper from W5

altogether to make certain that the device (U3) is not Toggling

or Self-Oscillating. Set the shorting jumper at W9 on Pins 1

and 2 (the left two pins) to route the REFCLK signal from J7

to Pin 69 of the AD9852. Finally, set the shorting jumper at

W3 to Pins 1 and 2 (the left two pins) to place the AD9852

in the single-ended clock mode.

Regardless of the origination, the signals arriving at the AD9852

are called the Reference Clock. If you choose to engage the

on-chip REFCLK Multiplier, this signal is the reference clock

for the REFCLK Multiplier and the REFCLK Multiplier output

becomes the SYSTEM CLOCK. If you choose to bypass the

REFCLK Multiplier, the reference clock that you have supplied is

directly operating the AD9852 and is, therefore, the system clock.

Three-state control or switch headers W11, W12, W14, and

W15 must be shorted to allow the provided software to control

the AD9852 evaluation board via the printer port connector J11.

If programming of the AD9852 is not to be provided by the host

PC via the ADI software, then headers W11, W12, W14, and W15

should be opened (shorting jumpers removed). This effectively

detaches the PC interface and allows the 40-pin header, J10, to

assume control without bus contention. Input signals on J10 going

to the AD9852 should be 3.3 V CMOS logic levels.

Low-Pass Filter Testing

The purpose of 2-pin headers W7 and W10 (associated with J1

and J2) are to allow the two 50

Ω, 120 MHz ﬁlters to be tested

during PCB assembly without interference from other circuitry

attached to the ﬁlter inputs. Normally, a shorting jumper will be

attached to each header to allow the DAC signals to be routed to the

ﬁlters. If the user wishes to test the ﬁlters, the shorting jumpers

at W7 and W10 should be removed and 50

Ω test signals applied

at J1 and J2 inputs to the 50

Ω elliptic ﬁlters. User should refer

to Figure 62 and the following sections to properly position the

remaining shorting jumpers.

Observing the Unﬁltered IOUT1 and the Unﬁltered IOUT2

DAC Signals

This allows the viewer to observe the unﬁltered DAC outputs at

J2 (the “I” signal) and J1 (the “Q” signal). The procedure below

simply routes the two 50

Ω terminated analog DAC outputs to

the BNC connectors and disconnects any other circuitry. The

“raw” DAC outputs will be a series of quantized (stepped) output

levels. The default 10 mA output current will develop a 0.5 V p-p

signal across the on-board 50

Ω termination. When connected

to an external 50

Ω input, the DAC will therefore develop 0.25 V p-p

due to the double termination.

1. Install shorting jumpers at W7 and W10.

2. Remove shorting jumper at W16.

3. Remove shorting jumper from 3-pin header W1.

4. Install shorting jumper on Pins 1 and 2 (bottom two pins) of

3-pin header W4.

Observing the Filtered IOUT1 and the Filtered IOUT2

This allows viewer to observe the ﬁltered sine DAC and control

DAC outputs at J4 (the sine signal) and J3 (the control DAC

signal). This places the 50

Ω (input and output Z) low-pass

ﬁlters in the I and Q DAC pathways to remove images and

aliased harmonics and other spurious signals above the dc to

approximately 120 MHz bandpass. These ﬁlters are designed

with the assumption that the system clock speed is at or near

maximum (300 MHz). If the system clock utilized is much less

than 300 MHz, for example, 200 MHz, unwanted DAC products

other than the fundamental signal will be passed by the low-

pass ﬁlters.

1. Install shorting jumpers at W7 and W10.

2. Install shorting jumper at W16.

3. Install shorting jumper on Pins 1 and 2 (bottom two pins) of

3-pin header W1.

4. Install shorting jumper on Pins 1 and 2 (bottom two pins) of

3-pin header W4.

5. Install shorting jumper on Pins 1 and 2 (top two pins) of 3-

pin header W2 and W8.

Observing the Filtered IOUT and the Filtered IOUTB

This allows viewer to observe only the ﬁltered sine DAC

outputs at J4 (the “true” signal) and J3 (the “complementary”

signal). This places the 120 MHz low-pass ﬁlters in the true

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