AD9852SLASHPCB datasheet(14/42 Pages) AD

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AD9852

–14–

REV. 0

USING THE AD9852

Internal and External Update Clock

This function is comprised of a bidirectional I/O pin, Pin 20, and a

programmable 32-bit down-counter. In order for programming

changes to be transferred from the I/O Buffer registers to the active

core of the DDS, a clock signal (low-to-high edge) must be externally

supplied to Pin 20 or internally generated by the 32-bit Update Clock.

An externally generated Update Clock is internally synchronized

with the system clock to prevent partial transfer of program

This mode gives the user complete control of when updated

program information becomes effective. The default mode is set

for internal update clock (Int Update Clk control register bit is

logic high). To switch to external update clock mode, the Int

Update Clk register bit must be set to logic low. The internal

update mode generates automatic, periodic update pulses whose

time period is set by the user.

An internally generated Update Clock can be established by

programming the 32-bit Update Clock registers (address 16–19

hex) and setting the Int Update Clk (address 1F hex) control

operates at the system clock/2 (150 MHz maximum) and counts

down from a 32-bit binary value (programmed by the user).

When the count reaches 0, an automatic I/O Update of the DDS

output or functions is generated. The update clock is routed

internally and externally on Pin 20 to allow users to synchronize

programming of update information with the update clock rate.

The time period between update pulses is given as:

(N+1)

× (SYSTEM CLOCK PERIOD × 2)

where N is the 32-bit value programmed by the user. Allow-

able range of N is from 1 to (2

32 –1). The internally generated

update pulse output on Pin 20 has a ﬁxed high time of eight system

clock cycles.

Shaped On/Off Keying

Allows user to control the ramp-up and ramp-down time of an

“on/off” emission from the I and Q DACs. This function is

used in “burst transmissions” of digital data to reduce the adverse

spectral impact of short, abrupt bursts of data. Users must ﬁrst

enable the digital multipliers by setting the OSK EN bit (con-

trol register address 20 hex) to logic high in the control register.

Otherwise, if the OSK EN bit is set low, the digital multipliers

responsible for amplitude control are bypassed and the I and Q

DAC outputs are set to full-scale amplitude. In addition to

setting the OSK EN bit, a second control bit, OSK INT (also at

address 20 hex) must be set to logic high. Logic high selects the

linear internal control of the output ramp-up or ramp-down

function. A logic low in the OSK INT bit switches control of

ABRUPT ON/OFF KEYING

SHAPED ON/OFF KEYING

Figure 31. Shaped On/Off Keying

the digital multipliers to user programmable 12-bit registers

allowing users to dynamically shape the amplitude transition in

practically any fashion. These 12-bit registers, labeled “Out-

put Shape Key” are located at addresses 21 through 24 hex in

Table V. The maximum output amplitude is a function of the

RSET resistor and is not programmable when OSK INT is enabled.

Next, the transition time from zero-scale to full-scale must

be programmed. The transition time is a function of two ﬁxed

elements and one variable. The variable element is the program

mable 8-bit RAMP RATE COUNTER. This is a down-counter

being clocked at the system clock rate (300 MHz max) that

outputs one pulse whenever the counter reaches zero. This pulse

is routed to a 12-bit counter that increments one LSB for every

pulse received. The outputs of the 12-bit counter are connected

to the 12-bit digital multiplier. When the digital multiplier has a

value of all zeros at its inputs, the input signal is multiplied by

zero, producing zero-scale. When the multiplier has a value of

all ones, the input signal is multiplied by a value of one, producing

full-scale. There are 4094 remaining fractional multiplier values

that will produce output amplitudes corresponding to their

binary values.

12-BIT DIGITAL

MULTIPLIER

(BYPASS MULTIPLIER)

OSK EN = 0

OSK EN = 1

OSK EN = 0

OSK EN = 1

DIGITAL

SIGNAL IN

USER PROGRAMMABLE

12-BIT Q-CHANNEL

MULTIPLIER

"OUTPUT SHAPE

KEY Q MULT"

OSK EN = 1

OSK EN = 0

12-BIT

COUNTER

8-BIT DOWN-

COUNTER

SYSTEM

CLOCK

SHAPING

KEYING PIN

SINE DAC

Figure 32. Block Diagram of Data Pathway of the Digital

Multiplier Section Responsible for Shaped Keying Function

The two ﬁxed elements are the clock period of the system clock,

which drives the Ramp Rate Counter, and the 4096 amplitude

steps between zero-scale and full-scale. To give an example,

assume that the System Clock of the AD9852 is 100 MHz (10 ns

period). If the Ramp Rate Counter is programmed for a minimum

count of five, it will take two system clock periods (one rising

edge loads the count-down value, the next edge decrements the

counter from five to four). The relationship of the 8-bit count-

down value to the time period between output pulses is given as:

(N+1)

× SYSTEM CLOCK PERIOD,

where N is the 8-bit count-down value. It will take 4096 of these

pulses to advance the 12-bit up-counter from zero-scale to full-

scale. Therefore, the minimum shaped keying ramp time for a

100 MHz system clock is 4096

× 6 × 10 ns = approximately

246

µs. The maximum ramp time will be 4096 × 256 × 10 ns =

approximately 10.5

µs.

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