AD9852SLASHPCB datasheet(23/42 Pages) AD

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AD9852

–23–

REV. 0

4. Continue chirp by reversing direction and returning to the

previous, or another, destination frequency in a linear or user-

directed manner. If this involves going down in frequency, a

negative 48-bit Delta Frequency Word (the MSB is set to “1”)

must be loaded into registers 10–15 hex. Any decreasing fre-

quency step of the Delta Frequency Word requires the MSB to

be set to logic high.

5. Continue chirp by immediately returning to the F1 beginning

frequency in a sawtooth fashion and repeat the previous chirp

process again. This is where CLR ACC1 control bit is used.

An automatic, repeating chirp can be setup using the 32-bit

Update Clock to issue CLR ACC1 commands at precise time

intervals. Adjusting the timing intervals or changing the Delta

Frequency Word will change the chirp range. It is incumbent

upon the user to balance the chirp duration and frequency

resolution to achieve the proper frequency range.

BPSK (Mode 100)

Binary, biphase, or bipolar phase shift keying is a means to rapidly

select between two preprogramming 14-bit output phase offsets

that will identically affect both the I and Q outputs of the AD9852.

The logic-state of Pin 29, BPSK pin, controls the selection of

Phase Adjust register number 1 or 2. When low, Pin 29 selects

HOLD

MODE

TW1

DFW

000 (DEFAULT)

RAMP RATE

011 (CHIRP)

DELTA FREQUENCY WORD

RAMP RATE

Figure 47. Illustration of HOLD Function

Phase Adjust register 1; when high, Phase Adjust register 2 is

selected. Figure 48 illustrates phase changes made to four cycles

of an output carrier.

Basic BPSK programming steps:

1. Program a carrier frequency into Frequency Tuning Word 1.

2. Program appropriate 14-bit phase words in Phase Adjust

registers 1 and 2.

3. Attach BPSK data source to Pin 29.

4. Activate I/O Update pulse when ready.

If phase shift keying is not the objective, but rather a broader

range of phase offsets is needed, the user should select the Single-

Tone mode and program Phase Adjust register 1 using the serial or

high-speed parallel programming bus.

I/O Port Buffers—100 MHz, 8-bit parallel or 10 MHz serial

loading, SPI-compatible. The programming mode is selected

externally via the serial/parallel (S/P Select) pin. I/O Buffers can

be written to, or read from, according to the signals supplied to

the Read (RDB) and Write pins (WRB) and the 6-bit address

(A0–A5) in the parallel mode or to CSB, SCLK and SDIO pins

in the Serial mode.

BPSK DATA

360

MODE

FTW1

PHASE ADJUST 1

000 (DEFAULT)

PHASE ADJUST 2

100 (BPSK)

270 DEGREES

90 DEGREES

PHASE AFTER

ONSET

PHASE BEFORE

ONSET

Figure 48. BPSK Mode

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