AD9852SLASHPCB datasheet(19/42 Pages) AD

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AD9852

–19–

REV. 0

Parallel register addresses 1A–1C hex comprise the 20-bit “Ramp

Rate Clock” registers. This is a count-down counter that outputs a

single pulse whenever the count reaches zero. The counter is

activated any time a logic level change occurs on FSK input

Pin 29. This counter is run at the System Clock Rate, 300 MHz

maximum. The time period between each output pulse is given as

(N+1)

× (SYSTEM CLOCK PERIOD)

where N is the 20-bit ramp rate clock value programmed by the

user. Allowable range of N is from 1 to (2

20 –1). The output of

this counter clocks the 48-bit Frequency Accumulator shown be-

low in Figure 39. The Ramp Rate Clock determines the amount

of time spent at each intermediate frequency between F1 and F2.

The counter stops automatically when the destination frequency

is achieved. The “dwell time” spent at F1 and F2 is determined

by the duration that the FSK input, Pin 29, is held high or low

after the destination frequency has been reached.

FREQUENCY

TUNING

WORD 1

20-BIT

RAMP RATE

CLOCK

48-BIT DELTA-

FREQUENCY

WORD

FREQUENCY

ACCUMULATOR

PHASE

ACCUMULATOR

OUT

ADDER

FSK

(PIN 29)

SYSTEM

CLOCK

FREQUENCY

TUNING

WORD 2

Figure 39. Block Diagram of Ramped FSK Function

Parallel register addresses 10–15 hex comprise the 48-bit, straight

binary, “Delta Frequency Word” registers. This 48-bit word

is accumulated (added to the accumulator’s output) every time

it receives a clock pulse from the ramp rate counter. The output

of this accumulator is then added to or subtracted from the F1

or F2 frequency word, which is then fed to the input of the 48-bit

Phase Accumulator that forms the numerical phase steps for the

sine and cosine wave outputs. In this fashion, the output frequency

MODE

TW1

TW2

FSK DATA

010 (RAMPED FSK)

000 (DEFAULT)

Figure 38. Ramped FSK Mode

is ramped up and down in frequency, according to the logic-

state of Pin 29. The rate at which this happens is a function of

the 20-bit ramp rate clock. Once the destination frequency is

achieved, the ramp rate clock is stopped, which halts the frequency

accumulation process.

Generally speaking, the Delta Frequency Word will be a much

smaller value as compared to that of the F1 or F2 tuning word.

For example, if F1 and F2 are 1 kHz apart at 13 MHz, the Delta

Frequency Word might be only 25 Hz.

Figure 41 shows that premature toggling causes the ramp to

immediately reverse itself and proceed at the same rate and resolu-

tion back to originating frequency.

The control register contains a Triangle bit at parallel register

address 1F hex. Setting this bit high in Mode 010 causes an

automatic ramp-up and ramp-down between F1 and F2 to occur

without having to toggle Pin 29 as shown in Figure 40. In fact,

the logic state of Pin 29 has no effect once the Triangle bit is set

high. This function uses the ramp-rate clock time period and the

delta-frequency-word step size to form a continuously sweeping

linear ramp from F1 to F2 and back to F1 with equal dwell times

at every frequency. Using this function, one can automatically

sweep from dc to the Nyquist limit or any other two frequencies

between dc and Nyquist.

MODE

TW1

TW2

FSK DATA

TRIANGLE

BIT

010 (RAMPED FSK)

Figure 40. Effect of Triangle Bit in Ramped FSK Mode

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