AD9852SLASHPCB datasheet(16/42 Pages) AD

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AD9852

–16–

REV. 0

Table I. REFCLK Multiplier Control Register Values

Multiplier Value

Ref Mult 4

Ref Mult 3

Ref Mult 2

Ref Mult 1

Ref Mult 0

400100

500101

600110

700111

801000

901001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

The REFCLK Multiplier function can be bypassed to allow

direct clocking of the AD9852 from an external clock source.

The system clock for the AD9852 is either the output of the

REFCLK Multiplier (if it is engaged) or the REFCLK inputs.

REFCLK may be either a single-ended or differential input by

setting Pin 64, DIFF CLK ENABLE, low or high respectively.

PLL Range Bit

The PLL Range Bit selects the frequency range of the REFCLK

Multiplier PLL. For operation from 200 MHz to 300 MHz

(internal system clock rate) the PLL Range Bit should be set to

Logic 1. For operation below 200 MHz, the PLL Range Bit

should be set to Logic 0. The PLL Range Bit adjusts the PLL

loop parameters for optimized phase noise performance within

each range.

Pin 61, PLL FILTER

This pin provides the connection for the external zero compen-

sation network of the PLL loop ﬁlter. The zero compensation

network consists of a 1.3 k

Ω resistor in series with a 0.01 µF

capacitor. The other side of the network should be connected to

as close as possible to Pin 60, AVDD. For optimum phase noise

performance the clock multiplier can be bypassed by setting the

“Bypass PLL” bit in control register address 1E.

Differential REFCLK Enable

A high level on this pin enables the differential clock Inputs,

REFCLOCK and REFCLOCKB (Pins 69 and 68 respec-

tively). The minimum differential signal amplitude required

is 800 mV p-p. The centerpoint or common-mode range of the

differential signal can range from 1.6 V to 1.9 V.

When Pin 64 (DIFF CLK ENABLE) is tied low, REFCLK

(Pin 69) is the only active clock input. This is referred to as

the single-ended mode. In this mode, Pin 68 (REFCLKB) should

be tied low or high, but not left floating.

Parallel/ Serial Programming Mode

Setting Pin 70 high invokes parallel mode, whereas setting Pin

70 low will invoke the serial programming mode. Please refer

to the text describing the serial and parallel programming

protocol contained in this data sheet for further information.

Two control bits located at address 20 hex in the Table V apply

only to the serial programming mode. LSB First when high,

dictates that serial data will be loaded starting with the LSB of

the word. When low (the default value), serial data is loaded

starting with the MSB of the word. SDO Active when high

indicates that the SDO pin, Pin 18, is dedicated to reading back

data from the AD9852 registers. When SDO Active is low

(default value), this indicates that the SDIO pin, Pin 19, acts

as a bidirectional serial data input and output pin and Pin 18

has no function in the serial mode.

DESCRIPTION OF AD9852 MODES OF OPERATION

There are ﬁve programmable modes of operation of the AD9852.

Selecting a mode requires that three bits in the Control Register

(parallel address 1F hex) be programmed as follows in Table II.

Table II. Mode Selection Table

Mode 2

Mode 1

Mode 0

Result

SINGLE-TONE

FSK

RAMPED FSK

CHIRP

BPSK

In each mode, engaging certain functions may or may not be

permitted. Shown in Table III is a listing of some important

functions and their availability for each mode.

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