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AD9852/PCB 数据表(PDF) 25 Page - Analog Devices

部件名 AD9852/PCB
功能描述  CMOS 300 MHz Complete-DDS
PDF  42 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9852/PCB 数据表(HTML) 25 Page - Analog Devices

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AD9852
–25–
REV. 0
Table V. Register Layout. Shaded Sections Comprise the Control Register
Parallel
Serial
Address
Address
AD9852 Register Layout
Default
Hex
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value
00
0
Phase Adjust Register #1 <13:8> (Bits 15, 14 don’t care)
Phase 1
00h
01
Phase Adjust Register #1 <7:0>
00h
02
1
Phase Adjust Register #2 <13:8:> (Bits 15, 14 don’t care)
Phase 2
00h
03
Phase Adjust Register #2 <7:0>
00h
04
2
Frequency Tuning Word 1 <47:0>
Frequency 1
00h
05
Frequency Tuning Word 1 <39:32>
00h
06
Frequency Tuning Word 1 <31:24>
00h
07
Frequency Tuning Word 1 <23:16>
00h
08
Frequency Tuning Word 1 <15:8>
00h
09
Frequency Tuning Word 1 <7:0>
00h
0A
3
Frequency Tuning Word 2 <47:40>
Frequency 2
00h
0B
Frequency Tuning Word 2 <39:32>
00h
0C
Frequency Tuning Word 2 <31:24>
00h
0D
Frequency Tuning Word 2 <23:16>
00h
0E
Frequency Tuning Word 2 <15:8>
00h
0F
Frequency Tuning Word 2 <7:0>
00h
10
4
Delta Frequency Word <47:40>
00h
11
Delta Frequency Word <39:32>
00h
12
Delta Frequency Word <31:24>
00h
13
Delta Frequency Word <23:16>
00h
14
Delta Frequency Word <15:8>
00h
15
Delta Frequency Word <7:0>
00h
16
5
Update Clock <31:24>
00h
17
Update Clock <23:16>
00h
18
Update Clock <15:8>
00h
19
Update Clock <7:0>
40h
1A
6
Ramp Rate Clock <19:16> (Bits 23, 22, 21, 20 don’t care)
00h
1B
Ramp Rate Clock <15:8>
00h
1C
Ramp Rate Clock <7:0>
00h
1D
7
Don’t
Don’t
Don’t
Comp PD
Reserved,
Control
DAC PD
DIG PD
00h
Care
Care
Care
Always
DAC PD
1E
Low
1F
Don’t
PLL
Bypass
Ref Mult 4
Ref Mult 3
Ref Mult 2
Ref Mult 1
Ref Mult 0
64h
Care
Range
PLL
20
CLR
CLR
Triangle
Don’t Care
Mode 2
Mode 1
Mode 0
Int Update
01h
ACC 1
ACC 2
Clk
Don’t
Bypass
OSK EN
OSK INT
Don’t
Don’t
LSB First
SDO
20h
Care
Inv
Care
Care
Active
Sinc
21
8
Output Shape Key I Mult <11:8> (Bits 15, 14, 13, 12 don’t care)
00h
22
Output Shape Key I Mult <7:0>
00h
23
9
Output Shape Key Q Mult <11:8> (Bits 15, 14, 13, 12 don’t care)
00h
24
Output Shape Key Q Mult <7:0>
00h
25
A
Output Shape Key Ramp Rate <7:0>
80h
26
B
QDAC <11:8> (Bits 15, 14, 13, 12 don’t care)
00h
27
QDAC <7:0>
(Data is required to be in twos-complement format)
00h



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