AD9852SLASHPCB datasheet(11/42 Pages) AD

11 / 42 page

AD9852

–11–

REV. 0

DAC CURRENT – mA

1015

2025

Figure 19. SFDR vs. DAC Current, 59.1 MHz AOUT, 300 MHz

EXTCLK

FREQUENCY – MHz

620

615

610

605

600

595

590

100

120

140

Figure 20. Supply Current vs. Output Frequency; Variation

Is Minimal as a Percentage and Heavily Dependent on

Tuning Word

FREQUENCY – Hz

–110

100

–115

–120

–125

–130

–135

–140

–145

–150

–155

10k

100k

80MHz

5MHz

a. Residual Phase Noise 300 MHz Direct Clocking

FREQUENCY – Hz

–110

100

–115

–120

–125

–130

–135

–140

–145

–150

–155

10k

100k

80MHz

5MHz

b. Residual Phase Noise, 300 MHz (10

× REFCLK Multiplier

Enabled)

Figure 18. Residual Phase Noise, EXTCLK = 300 MHz, REFCLK Multiplier Disabled/Enabled at 10

RISE TIME

1.04ns

500ps/DIV

232mV/DIV

INPUT

JITTER

[10.6ps RMS]

–33ps

0ps

+33ps

Figure 21. Typical Comparator Output Jitter, 40 MHz

AOUT, 300 MHz EXTCLK/REFCLK Multiplier Disabled

REF1 RISE

1.174ns

C1 FALL

1.286ns

CH1

500mV

M 500ps CH1

980mV

Figure 22. Comparator Rise/Fall Times

AD9852/PCB 数据表(PDF) 11 Page - Analog Devices

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