AD9852SLASHPCB datasheet(18/42 Pages) AD

18 / 42 page

AD9852

–18–

REV. 0

Unramped FSK (Mode 001)

When selected, the output frequency of the DDS is a function

of the values loaded into Frequency Tuning Word registers 1

and 2 and the logic level of Pin 29 (FSK/BPSK/HOLD). A logic

low on Pin 29 chooses F1 (frequency tuning word 1, parallel

address 4–9 hex) and a logic high chooses F2 (frequency tuning

word 2, parallel register address A–F hex). Changes in frequency

are phase-continuous and practically instantaneous. (Please refer to

pipeline delays in speciﬁcation table.) Other than F2 and Pin 29

becoming active, this mode is identical to single-tone.

The unramped FSK mode, Figure 36, is representative of

traditional FSK, RTTY (Radio Teletype) or TTY (Teletype)

transmission of digital data. Frequency transitions occur nearly

instantaneously from F1 to F2. This simple method works

extremely well and is the most reliable form of digital communica-

tion, but it is also wasteful of RF spectrum.

See the following Ramped FSK section for an alternative FSK

method that conserves bandwidth.

Ramped FSK (Mode = 010)

A method of FSK whereby changes from F1 to F2 are not

instantaneous but instead are accomplished in a frequency

sweep or “ramped” fashion. The “ramped” notation implies

that the sweep is linear. While linear sweeping or frequency

ramping is easily and automatically accomplished, it is only one

of many possibilities. Other frequency transition schemes may

be implemented by changing the ramp rate and ramp step size

“on-the-fly,” in piecewise fashion.

Frequency ramping, whether linear or nonlinear, necessitates

that many intermediate frequencies between F1 and F2 will be

output in addition to the primary F1 and F2 frequencies. Fig-

ures 37 and 38 graphically depict the frequency versus time

characteristics of a linear ramped FSK signal.

The purpose of ramped FSK is to provide better bandwidth

containment than traditional FSK by replacing the instantaneous

frequency changes with more gradual, user-deﬁned frequency

changes. The dwell time at F1 and F2 can be equal to or much

greater than the time spent at each intermediate frequency. The

user controls the dwell time at F1 and F2, the number of inter-

mediate frequencies and time spent at each frequency. Unlike

unramped FSK, ramped FSK requires the lowest frequency to be

loaded into F1 registers and the highest frequency into F2 registers.

Several registers must be programmed to instruct the DDS

regarding the resolution of intermediate frequency steps (48

bits) and the time spent at each step (20 bits). Furthermore, the

CLR ACC1 bit in the control register should be toggled (low-high-

low) prior to operation to assure that the frequency accumulator

is starting from an “all zeros” output condition. For piecewise,

nonlinear frequency transitions, it is necessary to reprogram the

registers while the frequency transition is in progress to affect the

desired response.

MODE

TW1

TW2

FSK DATA (PIN 29)

001 (FSK NO RAMP)

000 (DEFAULT)

Figure 36. Traditional FSK Mode

MODE

TW1

TW2

FSK DATA (PIN 29)

010 (RAMPED FSK)

000 (DEFAULT)

Figure 37. Ramped FSK Mode

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