AD9852SLASHPCB datasheet(15/42 Pages) AD

15 / 42 page

AD9852

–15–

REV. 0

Finally, changing the logic state of Pin 30, “shaped keying” will

automatically perform the programmed output envelope functions

when OSK INT is high. A logic high on Pin 30 causes the out-

puts to linearly ramp up to full-scale amplitude and hold until

the logic level is changed to low, causing the outputs to ramp

down to zero-scale.

Cosine DAC

The cosine DAC generates the 300 MSPS (maximum) cosine

output of the DDS. The maximum output amplitude is set

by the DAC RSET resistor at Pin 56. This is a current-out DAC

with a full-scale maximum output of 20 mA; however, a nomi-

nal 10 mA output current provides best spurious-free dynamic

range (SFDR) performance. The value of RSET = 39.93/IOUT,

where IOUT is in amps. DAC output compliance speciﬁcation lim-

its the maximum voltage developed at the outputs to –0.5 V to

+1 V. Voltages developed beyond this limitation will cause exces-

sive DAC distortion and possibly permanent damage. The user

must choose a proper load impedance to limit the output voltage

swing to the compliance limits. For best SFDR, both DAC outputs

should be terminated equally, especially at higher output fre-

quencies where harmonic distortion errors are more prominent.

The cosine DAC is preceded by inverse SIN(x)/x ﬁlters (a.k.a.

inverse sinc ﬁlter) that precompensate for DAC output amplitude

variations over frequency to achieve flat amplitude response from

dc to Nyquist. A digital multiplier follows the inverse sinc ﬁlters

to allow amplitude control, amplitude modulation and ampli-

tude shaped keying. The inverse sinc ﬁlter (address 20 hex, Bypass

Inv Sinc bit)) and digital multiplier (address 20 hex, OSK EN

bit) can be bypassed for power conservation by setting those bits

high. Both DACs can be powered down by setting the DAC

bit high (address 1D of control register) when not needed.

Cosine DAC outputs are designated as IOUT1 and IOUT1B,

Pins 48 and 49 respectively.

Control DAC

The 12-bit auxiliary, or control DAC can provide dc control

levels to external circuitry, generate ac signals, or duty cycle con-

trol, of the on-board comparator. The input twos complement

data is channeled through the serial or parallel interface to the

12-bit register (address 26 and 27 hex) at a maximum 100 MHz

data rate. This DAC is clocked at the system clock, 300 MSPS

(maximum), and has the same maximum output current capa-

bility as that of the cosine DAC. The single RSET resistor on the

AD9852 sets the full-scale output current for both cosine DAC

and the control DACs. The control DAC can be separately

powered down for power conservation when not needed by

setting the Control DAC POWER-DOWN bit high (address

1D hex). Control DAC outputs are designated as IOUT2 and

IOUT2B (Pins 52 and 51 respectively).

CENTER 50MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10MHz/

SPAN 100MHz

IMAGES

FUNDAMENTAL OUTPUT POWER DECREASES

WITH INCREASING FREQUENCY

Figure 33. Normal SIN(x)/x DAC Output Power Envelope

Filter

CENTER 50MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10MHz/

SPAN 100MHz

FUNDAMENTAL OUTPUT POWER IS

"FLAT" FROM DC TO 1/2 FCLK

Figure 34. Inverse SIN(x)/x (Inverse Sinc) Filter Engaged

Inverse SINC Function

This ﬁlter precompensates input data to the cosine DAC for

the SIN(x)/x roll-off function to allow wide bandwidth signals

(such as QPSK) to be output from the DACs without appreciable

amplitude variations that will cause increased EVM (error vector

magnitude). The inverse SINC function may be bypassed to

signiﬁcantly reduce power consumption, especially at higher

clock speeds. Inverse sinc is engaged by default and is bypassed

by bringing the “Bypass Inv Sinc” bit high in control register 20

(hex) in Table V.

REFCLK Multiplier

This is a programmable PLL-based reference clock multiplier

that allows the user to select an integer clock multiplying value

over the range of 4

× to 20× by which the REFCLK input will be

multiplied. Use of this function allows users to input as little as

15 MHz to produce a 300 MHz internal system clock. Five bits

in control register 1E hex set the multiplier value as follows in

Table I.

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