WM8953ECSSLASHRV datasheet(48/100 Pages) WOLFSON

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WM8953

Production Data

PD, January 2009, Rev 4.0

PLL LOCK OUTPUT

An internal signal used to indicate the lock status of the PLL can be output to a GPIO pin or used to

trigger an Interrupt event. The polarity of the PLL Lock indication may be controlled by register bit

PLL_LCK_POL. Note that this polarity inversion bit applies to the Interrupt register behaviour only; it

does not affect the direct GPIO output of the PLL Lock function. The associated interrupt event may

be masked or enabled by register bit PLL_LCK_IRQ_ENA. The PLL Lock status bit in the IRQ

more details of the Interrupt function.

If direct output of the PLL Lock status bit is required to the external pins of the WM8953, the following

•

AIF_TRIS = 0

•

GPIOn_SEL = 0100 for the selected PLL Lock status output pin

•

GPIOn_PU = 0 for the selected PLL Lock status output pin

•

GPIOn_PD = 0 for the selected PLL Lock status output pin

The register fields used to configure the PLL Lock GPIO function are described in Table 28.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R23 (17h)

PLL_LCK_POL

(rw)

PLL Lock polarity

0 = Non-inverted

1 = Inverted

R22 (16h)

PLL_LCK_IRQ_

ENA

PLL Lock IRQ Enable

0 = disabled

1 = enabled

Table 28 PLL Lock GPIO Control

The PLL Lock function operates according to the following truth table:

LABEL

VALUE

DESCRIPTION

PLL Lock output

PLL not Locked

PLL Lock output

PLL Locked

Table 29 Truth Table for GPIO Output of PLL Lock Function

LOGIC '1' AND LOGIC '0' OUTPUT

The GPIO pins can be programmed to drive a logic high or logic low signal. The following register

settings are required:

•

AIF_TRIS = 0

•

GPIOn_SEL = 0010 for each Logic ‘0’ output pin

•

GPIOn_SEL = 0011 for each Logic ‘1’ output pin

•

GPIOn_PU = 0 for each Logic ‘0’ or Logic ‘1’ GPIO pin

•

GPIOn_PD = 0 for each Logic ‘0’ or Logic ‘1’ GPIO pin

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