 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
WM8953ECS/RV 数据表(PDF) 22 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8953ECS/RV 数据表(HTML) 22 Page - Wolfson Microelectronics plc |
|
|
22 / 100 page  WM8953 Production Data w PD, January 2009, Rev 4.0 22 CONTROL INTERFACE TIMING – 4-WIRE MODE 4-wire mode supports readback via SDOUT which is available as a GPIO pin function. Figure 9 Control Interface Timing – 4-Wire Serial Control Mode (Write Cycle) CSB SCLK SDOUT t DL LSB Figure 10 Control Interface Timing – 4-Wire Serial Control Mode (Read Cycle) Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, DGND=AGND=0V, TA =+25 oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB falling edge tCSU 40 ns SCLK falling edge to CSB rising edge tCHO 40 ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL 80 ns SCLK pulse width high tSCH 80 ns SDIN to SCLK set-up time tDSU 40 ns SDIN to SCLK hold time tDHO 10 ns SDOUT propagation delay from SCLK rising edge tDL 10 ns Pulse width of spikes that will be suppressed tps 0 5 ns SCLK falling edge to SDOUT transition tDL 40 ns |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
