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WM8953ECS/RV 数据表(PDF) 21 Page - Wolfson Microelectronics plc |
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WM8953ECS/RV 数据表(HTML) 21 Page - Wolfson Microelectronics plc |
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21 / 100 page  Production Data WM8953 w PD, January 2009, Rev 4.0 21 CONTROL INTERFACE TIMING – 3-WIRE MODE 3-wire mode is selected by connecting the MODE pin high. Figure 7 Control Interface Timing – 3-Wire Serial Control Mode (Write Cycle) CSB SCLK SDOUT t DL LSB Figure 8 Control Interface Timing – 3-Wire Serial Control Mode (Read Cycle) Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, DGND=AGND=0V, TA=+25 oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information CSB falling edge to SCLK rising edge tCSU 40 ns SCLK falling edge to CSB rising edge tCHO 40 ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL 80 ns SCLK pulse width high tSCH 80 ns SDIN to SCLK set-up time tDSU 40 ns SDIN to SCLK hold time tDHO 10 ns Pulse width of spikes that will be suppressed tps 0 5 ns SCLK falling edge to SDOUT transition tDL 40 ns |
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