WM8953ECSSLASHRV datasheet(60/100 Pages) WOLFSON

部件名	WM8953ECS/RV

功能描述	Low Power Stereo ADC with PLL and TDM Interface

PDF	100 Pages

Scroll/Zoom	100%

制造商	WOLFSON [Wolfson Microelectronics plc]

网页	http://www.wolfsonmicro.com

标志

60 / 100 page

WM8953

Production Data

PD, January 2009, Rev 4.0

In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising

edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of ADCLRC. Right channel

data immediately follows left channel data. Depending on word length, BCLK frequency and sample

rate, there may be unused BCLK cycles between the LSB of the right channel data and the next

sample.

In device master mode, the ADCLRC output will resemble the frame pulse shown in Figure 38 and

Figure 39. In device slave mode, Figure 40 and Figure 41, it is possible to use any length of frame

pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK

period before the rising edge of the next frame pulse.

Figure 38 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master)

Figure 39 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master)

Figure 40 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave)

WM8953ECS/RV 数据表(PDF) 60 Page - Wolfson Microelectronics plc