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WM8953ECS/RV 数据表(PDF) 16 Page - Wolfson Microelectronics plc

部件名 WM8953ECS/RV
功能描述  Low Power Stereo ADC with PLL and TDM Interface
PDF  100 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8953ECS/RV 数据表(HTML) 16 Page - Wolfson Microelectronics plc

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WM8953
Production Data
w
PD, January 2009, Rev 4.0
16
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 2 System Clock Timing Requirements
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=3.3V, DGND=AGND=0V, TA = +25
oC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK cycle time
TMCLKY
33.33
ns
MCLK duty cycle
= TMCLKH/TMCLKL
60:40
40:60
MCLK
t
MCLKL
t
MCLKH
t
MCLKY



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