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WM8953ECS/RV 数据表(PDF) 87 Page - Wolfson Microelectronics plc |
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WM8953ECS/RV 数据表(HTML) 87 Page - Wolfson Microelectronics plc |
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87 / 100 page  Production Data WM8953 w PD, January 2009, Rev 4.0 87 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 12:11 MCLK_DIV [1:0] 00b SYSCLK Pre-divider. Clock source (MCLK or PLL output) will be divided by this value to generate SYSCLK. 00 = Divide SYSCLK by 1 01 = Reserved 10 = Divide SYSCLK by 2 11 = Reserved 10 MCLK_INV 0b MCLK Invert 0 = Master clock not inverted 1 = Master clock inverted 9:8 00b Reserved - Do Not Change 7:5 ADC_CLKDIV [2:0] 000b ADC Sample Rate Divider 000 = SYSCLK / 1.0 001 = SYSCLK / 1.5 010 = SYSCLK / 2.0 011 = SYSCLK / 3.0 100 = SYSCLK / 4.0 101 = SYSCLK / 5.5 110 = SYSCLK / 6.0 111= Reserved 4:0 00000b Reserved - Do Not Change 15 AIF_MSTR 0b Audio Interface Master Mode Select 0 = Slave mode 1 = Master mode 14:12 000b Reserved - Do Not Change 11 ADCLRC_DIR 0b ADCLRC Direction (Forces ADCLRC clock to be output in slave mode) 0 = ADCLRC normal operation 1 = ADCLRC clock output enabled R08 (08h) Audio Interface (3) 10:0 ADCLRC_RATE [10:0] 040h ADCLRC Rate ADCLRC clock output = BCLK / ADCLRC_RATE Integer (LSB = 1) Valid from 8..2047 15:14 00b Reserved - Do Not Change 13 AIF_TRIS 0b Audio Interface and GPIO Tristate 0 = Audio interface and GPIO pins operate normally 1 = Tristate all audio interface and GPIO pins 12 0b Reserved - Do Not Change R09 (09h) Audio Interface (4) 11:0 040h Reserved - Do Not Change 15:11 00000b Reserved - Do Not Change 10 AIF_LRCLKRATE 0b LRCLK Rate 0 = Normal mode (256 * fs) 1 = USB mode (272 * fs) 9:8 00b Reserved - Do Not Change R10 (0Ah) LRCLK Rate 7:0 04h Reserved - Do Not Change R11 (0Bh) 15:0 0060h Reserved - Do Not Change R12 (0Ch) 15:0 0060h Reserved - Do Not Change R13 (0Dh) 15:0 0000h Reserved - Do Not Change 15:9 00h Reserved - Do Not Change 8 ADC_HPF_ENA 1b ADC Digital High Pass Filter Enable 0 = disabled 1 = enabled R14 (0Eh) ADC Control 7 0b Reserved - Do Not Change |
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