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M95128-RMB6TG 数据表(PDF) 14 Page - STMicroelectronics

部件名 M95128-RMB6TG
功能描述  128-Kbit serial SPI bus EEPROM with high-speed clock
PDF  49 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M95128-RMB6TG 数据表(HTML) 14 Page - STMicroelectronics

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Operating features
M95128-W M95128-R M95128-DF
14/49
Doc ID 5798 Rev 16
5.1.4
Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum
VCC operating voltage defined under Operating conditions in Section 9: DC and AC
parameters), the device must be:
deselected (Chip Select S should be allowed to follow the voltage applied on VCC),
in Standby Power mode (there should not be any internal write cycle in progress).
5.2
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to ICC1, as specified in DC characteristics (see Section 9: DC and AC parameters).
5.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial
Data Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
been in progress.(a)(b)
Figure 7.
Hold condition activation
The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 7).
a.
This resets the internal logic, except the WEL and WIP bits of the Status Register.
b.
In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
ai02029E
c
HOLD
Hold
condition
Hold
condition



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