M95128-RMB6TG datasheet(15/49 Pages) STMICROELECTRONICS

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M95128-W M95128-R M95128-DF

Operating features

Doc ID 5798 Rev 16

15/49

The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)

is already low.

Figure 7 also shows what happens if the rising and falling edges are not timed to coincide

with Serial Clock (C) being low.

5.4

Status Register

The Status Register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a

detailed description of the Status Register bits.

5.5

Data protection and protocol control

The device features the following data protection mechanisms:

●

Before accepting the execution of the Write and Write Status Register instructions, the

device checks whether the number of clock pulses comprised in the instructions is a

multiple of eight.

●

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit.

●

The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of

the memory as read-only.

●

The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the

Status Register.

For any instruction to be accepted, and executed, Chip Select (S) must be driven high after

the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising

edge of Serial Clock (C).

Two points should be noted in the previous sentence:

●

The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth

bit of a data byte, depending on the instruction (except for Read Status Register

(RDSR) and Read (READ) instructions).

●

The “next rising edge of Serial Clock (C)” might (or might not) be the next bus

transaction for some other device on the SPI bus.

Table 2.

Write-protected block size

Status Register bits

Protected block

Protected array addresses

BP1

BP0

none

Upper quarter

3000h - 3FFFh

Upper half

2000h - 3FFFh

Whole memory

0000h - 3FFFh plus Identification page

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