M95128-RMB6TG datasheet(30/49 Pages) STMICROELECTRONICS

部件名	M95128-RMB6TG

功能描述	128-Kbit serial SPI bus EEPROM with high-speed clock

PDF	49 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

30 / 49 page

Power-up and delivery state

M95128-W M95128-R M95128-DF

30/49

Doc ID 5798 Rev 16

Power-up and delivery state

7.1

Power-up state

After power-up, the device is in the following state:

●

Standby power mode,

●

deselected (after power-up, a falling edge is required on Chip Select (S) before any

instructions can be started),

●

not in the Hold condition,

●

the Write Enable Latch (WEL) is reset to 0,

●

Write In Progress (WIP) is reset to 0.

The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous

power-down (they are non-volatile bits).

7.2

Initial delivery state

The device is delivered with the memory array bits and identification page bits set to all 1s

(each byte = FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and

BP0) bits are initialized to 0.

M95128-RMB6TG 数据表(PDF) 30 Page - STMicroelectronics