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M95128-RMB6TG 数据表(PDF) 37 Page - STMicroelectronics

部件名 M95128-RMB6TG
功能描述  128-Kbit serial SPI bus EEPROM with high-speed clock
PDF  49 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M95128-RMB6TG 数据表(HTML) 37 Page - STMicroelectronics

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M95128-W M95128-R M95128-DF
DC and AC parameters
Doc ID 5798 Rev 16
37/49
Table 19.
AC characteristics (M95128-W, device grade 6)
Test conditions specified in
Table 9 and Table 12
Previous(1)
and new
products
CL ≤100 pF
1.
Previous products are identified by process letters A.
New products(2)
CL ≤30 pF
2.
New products are M95128 devices identified by process letter K.
Unit
Vcc ≥ 2.5V
Vcc ≥ 4.5V
Symbol
Alt.
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
fC
fSCK
Clock frequency
D.C.
5
D.C.
10
D.C.
20
MHz
tSLCH
tCSS1 S active setup time
90
30
15
ns
tSHCH
tCSS2 S not active setup time
90
30
15
ns
tSHSL
tCS
S deselect time
100
40
20
ns
tCHSH
tCSH
S active hold time
90
30
15
ns
tCHSL
S not active hold time
90
30
15
ns
tCH
(3)
3.
tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
tCLH
Clock high time
90
40
20
ns
tCL
(3)
tCLL
Clock low time
90
40
20
ns
tCLCH
(3)
tRC
Clock rise time
1
2
2
µs
tCHCL
(3)
tFC
Clock fall time
1
2
2
µs
tDVCH
tDSU
Data in setup time
20
10
5
ns
tCHDX
tDH
Data in hold time
30
10
10
ns
tHHCH
Clock low hold time after
HOLD not active
70
30
15
ns
tHLCH
Clock low hold time after
HOLD active
40
30
15
ns
tCLHL
Clock low setup time
before HOLD active
00
0
ns
tCLHH
Clock low setup time
before HOLD not active
00
0
ns
tSHQZ
(4)
4.
Characterized only, not tested in production.
tDIS
Output disable time
100
40
20
ns
tCLQV
tV
Clock low to output valid
60
40
20
ns
tCLQX
tHO
Output hold time
0
0
0
ns
tQLQH
(4)
tRO
Output rise time
50
20
10
ns
tQHQL
(4)
tFO
Output fall time
50
20
10
ns
tHHQV
tLZ
HOLD high to output
valid
50
40
20
ns
tHLQZ
(4)
tHZ
HOLD low to output
High-Z
100
40
20
ns
tW
tWC
Write time
5
5
5
ms



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