W25Q40BLSVIP datasheet(55/74 Pages) WINBOND

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W25Q40BL

Publication Release Date: May 04, 2012

- 55 -

Revision D

7.2.37 Erase Security Registers (44h)

The W25Q40BL offers three 256-byte Security Registers which can be erased and programmed

individually. These registers may be used by the system manufacturers to store security and other

important information separately from the main memory array.

The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable

instruction must be executed before the device will accept the Erase Security Register Instruction (Status

instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the three security registers.

ADDRESS

A23-16

A15-12

A11-8

A7-0

Security Register #1

00h

0 0 0 1

0 0 0 0

Don’t Care

Security Register #2

00h

0 0 1 0

0 0 0 0

Don’t Care

Security Register #3

00h

0 0 1 1

0 0 0 0

Don’t Care

The Erase Security Register instruction sequence is shown in figure 35. The /CS pin must be driven high

after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.

After /CS is driven high, the self-timed Erase Security Register operation will commence for a time

duration of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read

Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is

a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept

other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch

(WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits LB[3:1] in the Status

security register will be permanently locked, Erase Security Register instruction to that register will be

ignored (See 7.1.9 for detail descriptions).

Figure 35. Erase Security Registers Instruction Sequence

Instruction (44h)

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