W25Q40BLSVIP datasheet(23/74 Pages) WINBOND

23 / 74 page

W25Q40BL

To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or

sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be

executed. If /CS is driven high after the eighth clock (compatible with the 25X series) the CMP and QE bits

will be cleared to 0.

During non-volatile Status Register write operation (06h combined with 01h), after /CS is driven high, the

self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).

While the Write Status Register cycle is in progress, the Read Status Register instruction may still be

accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle

and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status

During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the

Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC

Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.

Please refer to 10.1 for detailed Status Register Bit descriptions. Factory default for all status Register bits

are 0.

15 14 13 12 11 10

Status Register 1

Status Register 2

15 14 13 12 11 10

Status Register 1

Status Register 2

Figure 8. Write Status Register Instruction Sequence Diagram

Publication Release Date: May 04, 2012

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Revision D

W25Q40BLSVIP 数据表(PDF) 23 Page - Winbond