W25Q40BLSVIP datasheet(16/74 Pages) WINBOND

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W25Q40BL

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7.2 INSTRUCTIONS

The instruction set of the W25Q40BL consists of thirty five basic instructions that are fully controlled

through the SPI bus (see Instruction Set table1-3). Instructions are initiated with the falling edge of Chip

Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI

input is sampled on the rising edge of clock with most significant bit (MSB) first.

Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data

bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the

rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in figures 4

through 37. All read instructions can be completed after any clocked bit. However, all instructions that

Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been

clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent

writes. Additionally, while the memory is being programmed or erased, or when the Status Register is

being written, all instructions except for Read Status Register will be ignored until the program or erase

cycle has completed.

7.2.1

Manufacturer and Device Identification

MANUFACTURER ID

(MF7-MF0)

Winbond Serial Flash

EFh

Device ID

(ID7-ID0)

(ID15-ID0)

Instruction

ABh, 90h, 92h, 94h

9Fh

W25Q40BL

12h

4013h

W25Q40BLSVIP 数据表(PDF) 16 Page - Winbond