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PSD813F2 数据表(PDF) 115 Page - STMicroelectronics

部件名 PSD813F2
功能描述  Flash in-system programmable (ISP) peripherals
PDF  128 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PSD813F2 数据表(HTML) 115 Page - STMicroelectronics

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PSD8XXFX
AC/DC parameters
Doc ID 7833 Rev 7
115/128
Table 69.
ISC timing (3 V devices)
Symbol
Parameter
Conditions
-12
-15
-20
Unit
Min Max Min Max Min Max
tISCCF
Clock (TCK, PC1) frequency (except for
PLD)
(1)
12
10
9
MHz
tISCCH
Clock (TCK, PC1) high time (except for
PLD)
(1)
40
45
51
ns
tISCCL
Clock (TCK, PC1) low time (except for
PLD)
(1)
40
45
51
ns
tISCCFP
Clock (TCK, PC1) frequency (PLD only)
(2)
22
2
MHz
tISCCHP
Clock (TCK, PC1) high time (PLD only)
(2)
240
240
240
ns
tISCCLP
Clock (TCK, PC1) low time (PLD only)
(2)
240
240
240
ns
tISCPSU
ISC port setup time
12
13
15
ns
tISCPH
ISC port hold up time
5
5
5
ns
tISCPCO
ISC port clock to output
30
36
40
ns
tISCPZV
ISC port high-Impedance to valid Output
30
36
40
ns
tISCPVZ
ISC port valid Output to high-Impedance
30
36
40
ns
1.
For non-PLD Programming, Erase or in ISC by-pass mode.
2.
For program or erase PLD only.
Table 70.
Power-down timing (5 V devices)
Symbol
Parameter
Conditions
-70
-90
-15
Unit
Min Max Min
Max Min Max
tLVDV
ALE access time from Power-down
80
90
150
ns
tCLWH
Maximum delay from APD Enable to
Internal PDN valid signal
Using CLKIN
(PD1)
15 * tCLCL
(1)
µs
1.
tCLCL is the period of CLKIN (PD1).
Table 71.
Power-down timing (3 V devices)
Symbol
Parameter
Conditions
-12
-15
-20
Unit
Min Max Min
Max Min Max
tLVDV
ALE access time from Power-down
145
150
200
ns
tCLWH
Maximum Delay from APD Enable to
Internal PDN valid Signal
Using CLKIN
(PD1)
15 * tCLCL
(1)
µs
1.
tCLCL is the period of CLKIN (PD1).
Obsolete
Product(s)
- Obsolete
Product(s)



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