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STM32F103RG 数据表(PDF) 60 Page - STMicroelectronics |
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STM32F103RG 数据表(HTML) 60 Page - STMicroelectronics |
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60 / 120 page  Electrical characteristics STM32F103xF, STM32F103xG 60/120 Doc ID 16554 Rev 3 5.3.8 PLL characteristics The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 28. PLL characteristics Symbol Parameter Value Unit Min Typ Max(1) 1. Based on characterization, not tested in production. fPLL_IN PLL input clock(2) 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 18.0 25 MHz PLL input clock duty cycle 40 - 60 % fPLL_OUT PLL multiplier output clock 16 - 72 MHz tLOCK PLL lock time - - 200 µs Jitter Cycle-to-cycle jitter - - 300 ps Table 29. Flash memory characteristics Symbol Parameter Conditions Min Typ Max(1) 1. Guaranteed by design, not tested in production. Unit tprog 16-bit programming time TA = –40 to +105 °C 40 52.5 70 µs tERASE Page (2 KB) erase time TA = –40 to +105 °C 20 - 40 ms tME Mass erase time TA = –40 to +105 °C 20 - 40 ms IDD Supply current Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V -- 28 mA Write mode fHCLK = 72 MHz, VDD = 3.3 V -- 7 mA Erase mode fHCLK = 72 MHz, VDD = 3.3 V -- 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V - - 50 µA Vprog Programming voltage 2 - 3.6 V |
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