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STM32F103RG 数据表(PDF) 72 Page - STMicroelectronics |
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STM32F103RG 数据表(HTML) 72 Page - STMicroelectronics |
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72 / 120 page ![]() Electrical characteristics STM32F103xF, STM32F103xG 72/120 Doc ID 16554 Rev 3 Figure 29. Synchronous non-multiplexed PSRAM write timings Table 39. Synchronous non-multiplexed PSRAM write timings(1) 1. CL = 15 pF. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 27.6 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 0.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 1.5 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0.5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 1.5 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1.5 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 2.5 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0.5 - ns |
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