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STM32F103RG 数据表(PDF) 87 Page - STMicroelectronics |
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STM32F103RG 数据表(HTML) 87 Page - STMicroelectronics |
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87 / 120 page  STM32F103xF, STM32F103xG Electrical characteristics Doc ID 16554 Rev 3 87/120 Output voltage levels Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 50. Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL (1) 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Output low level voltage for an I/O pin when 8 pins are sunk at same time TTL port(3) IIO = +8 mA 2.7 V < VDD < 3.6 V -0.4 V VOH (2) 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - VOL (1) Output low level voltage for an I/O pin when 8 pins are sunk at same time CMOS port(3) IIO =+ 8mA 2.7 V < VDD < 3.6 V 3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. -0.4 V VOH (2) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.4 - VOL (1)(4) 4. Based on characterization data, not tested in production. Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +20 mA 2.7 V < VDD < 3.6 V -1.3 V VOH (2)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–1.3 - VOL (1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +6 mA 2 V < VDD < 2.7 V -0.4 V VOH (2)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - |
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