STM32F103RG datasheet(104/120 Pages) STMICROELECTRONICS

104 / 120 page

Electrical characteristics

STM32F103xF, STM32F103xG

104/120

Doc ID 16554 Rev 3

Figure 56.

Typical connection diagram using the ADC

Refer to Table 62 for the values of RAIN, RADC and CADC.

Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy

this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 57 or Figure 58,

depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be

ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 57.

Power supply and reference decoupling (VREF+ not connected to VDDA)

VREF+ and VREF– inputs are available only on 100-pin packages.

ai14150c

STM32F103xx

VDD

AINx

IL±1 µA

0.6 V

RAIN(1)

Cparasitic

VAIN

0.6 V

RADC(1)

12-bit

converter

CADC(1)

Sample and hold ADC

converter

VREF+

(see note 1)

STM32F103xx

VDDA

VSSA /VREF–

(see note 1)

1 µF // 10 nF

ai14388b

STM32F103RG 数据表(PDF) 104 Page - STMicroelectronics

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