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AS8510-ASSP 数据表(PDF) 27 Page - ams AG |
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AS8510-ASSP 数据表(HTML) 27 Page - ams AG |
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27 / 47 page  www.ams.com/AS8510 Revision 3.5 26 - 46 AS8510 Datasheet - Detailed Descr i p ti on 7.8.5 SPI Interface Timing Table 32. SPI Interface Timing Symbol Parameter Conditions Min Typ Max Units General BRSPI Bit rate 1 Mbps TSCLKH Clock high time 400 ns TSCLKL Clock low time 400 ns Write timing tDIS Data in setup time 20 ns tDIH Data in hold time 20 ns TCSH CS hold time 20 ns Read timing tDOD Data out delay 80 ns tDOHZ Data out to high impedance delay Time for the SPI to release the SDO bus 80 ns Timing parameters when entering 4-Wire SPI mode (for determination of CLK polarity) tCPS Clock setup time (CLK polarity) Setup time of SCLK with respect to CS falling edge 20 ns tCPHD Clock hold time (CLK polarity) Hold time of SCLK with respect to CS falling edge 20 ns |
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