| 数据搜索系统,热门电子元器件搜索 |
|
AS8510-ASSP 数据表(PDF) 40 Page - ams AG |
|
|
|||||||||||||||||||||||||||||
AS8510-ASSP 数据表(HTML) 40 Page - ams AG |
|
40 / 47 page ![]() www.ams.com/AS8510 Revision 3.5 39 - 46 AS8510 Datasheet - Detailed Descr i p ti on Table 34 provides valid combinations of Modulator clock, Chopper clock and Decimation R1 and the corresponding values of TDATA_STATUS_RD and TADC. 7.9.3 Soft-reset of Device Using Bit D[7] of Reset Register 0x09 It is possible to soft-reset the device by writing “0” into D[7] bit of Reset Register at 0x09. On applying soft-reset, the device enters into initialization state and D[6] bit changes back to “1”. The duration period of Initialization is 500 μsec, and, during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and activation should be carried out only after the initialization period. See Figure 17 for the timing details of the sequence of device initialization on soft-reset. Figure 17. AS8510 Device Initialization Sequence at Soft-reset 7.9.4 Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09 Measurement path also can be reset by using D[6] bit of Reset Register at 0x09. On applying soft-reset only signal measurement path registers will be reset. For applying this reset, device should be in STOP state. If the device is working with external clock, at the time of soft-reset the clock needs to be disabled. Table 34. Valid Combinations of Modulator Clock, Chopper Clock and Decimation Ratio R1 Modulator Clock Chopper Frequency CHOP_CLK Decimation Ratio R1 TDATA_STATUS_RD TADC R2/(2*CHOP_CLK) for R2=4 1.024MHz 2KHz 64 1usec * 64 * [4 - 2.5] = 96usec 1mSec 2.048MHz 2KHz 64 0.5usec * 64 * [8 - 2.5] = 176usec 1mSec 2.048MHz 2KHz 128 0.5usec * 128 * [4 - 2.5] = 96usec 1mSec 2.048MHz 4KHz 64 0.5usec * 64 * [4 - 2.5] = 48usec 0.5mSec DATA-N DATA-N+1 D4 D1 D2 D3 D4 D1 TDATA_STATUS_RD TDATA_VALID TDATA_INVALID Re-Configure Device Start ADC INT CHOP_CLK Channel Data Register 0x0000 DATA1 DATA2 D1 D2 D 3 D4 D1 D2 D3 D4 D1 D2 D3 D4 500µS 1.5mS TDATA_STATUS_RD TDATA_VALID TDATA_INVALID Soft Reset UsingD7 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |