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AS8510

Datasheet - Detailed Descr i p ti on

7.9.5

Reconfiguring Gain Setting of PGA

Only PGA gain settings can be changed dynamically while ADC conversions are in progress. When PGA gain settings are changed, the first

sample from the ADC is invalid. Ignore the first interrupt after the gain re-configuration. Valid data starts from the second interrupt onwards.

Figure 18. AS8510 - Re-configuration of Gain Setting of PGA

7.9.6 Configuring the Device During Normal Mode

Following registers can be programmed dynamically when the device is in operational mode (Normal mode).



ACH_CTL_REG address is 0x17 for channel selection on the voltage measurement path



PGA_CTL_REG address is 0x13 for gain setting



PD_CTL_REG2 address is 0x15 for PGA Bypass



ISC_CTL_REG address is 0x18 for current source programmability

During the operation (Normal mode) of the device, if any of the registers need to be programmed or changed other than the above mentioned

registers, then it is required to STOP the device by writing into MOD_CTL_REG “STOP” bit and configure the device as per the requirements and

start the device.

DATA-N

DATA-N+1

D4

D1

D2

D3

D4

INT

CHOP_CLK

Channel Data

Register

DATA1

DATA2

D2

D3

D4

D1

D2

D3

D4

D1

D2

D3

D4

D1

GainRe-Configuration canbe

carried out in this slot, skip next

interrupt andChannel Data.

ReadChannel

datainthisslot

VALID

DATA