CS4630

DS445PP1

7

PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V)

Notes: 15. For Active/Float measurements, the Hi-Z or “off” state is when the total current delivered is less than or

equal to the leakage current. Specification is guaranteed by design, not production tested.

16. RST# is asserted and de-asserted asynchronously with respect to PCICLK.

17. All output drivers are asynchronously floated when RST# is active.

18. REQ# and GNT# are point to point signals. All other PCI signals are considered bused signals.

Parameter

Symbol

Min

Max

Unit

PCICLK cycle time

30

-

ns

PCICLK high time

11

-

ns

PCICLK low time

11

-

ns

PCICLK to signal valid delay - bused signals

(Note 18)

211

ns

PCICLK to signal valid delay - point to point

(Note 18)

212

ns

Float to active delay

(Note 15)

1-

ns

Active to Float delay

(Note 15)

-28

ns

Input Set up Time to PCICLK - bused signals

(Note 18)

7-

ns

Input Set up Time to PCICLK - point to point

(Note 18)

10, 12

-

ns

Input hold time for PCICLK

0-

ns

Reset active time after PCICLK stable

(Note 16)

100

-

µs

Reset active to output float delay

(Notes 15, 16, 17)

-30

ns

PCICLK

RST#

OUTPUTS

Hi-Z

INPUTS

Valid

Input

OUTPUTS

Valid

Figure 2. PCI Timing Measurement Conditions