CS4630 datasheet(24/38 Pages) CIRRUS

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CS4630

DS445PP1

8. GENERAL PURPOSE I/O PINS

Many of the CS4630 signal pins are internally mul-

tiplexed to serve different functions depending on

the environment in which the device is being used.

Several of the CS4630 signal pins may be used as

general purpose I/O pins when not required for oth-

er specific functions in a given application.

8.1

EGPIO

In addition to the GPIO pins on the CS4630, ex-

tended general purpose I/O has been added. Four

EGPIO pins are not multiplexed, EGPIO[7, 2:0];

whereas; EGPIO[6:3] are shared with the asyn-

chronous serial port. When this second async. seri-

al port is not used, all the EGPIO pins are available.

These pins have extended functionality in that any

EGPIO pin can be programmed to cause a power

management wake-up event on the PME# signal.

These pins also can be programmed as:

• input or output,

• edge or level sensitive (sticky),

• active high or low input,

• CMOS or open-drain output

9. ZV PORT SERIAL INTERFACE

The ZV PORT interface consists of three input

pins: ZLRCK, ZSCLK, and ZSDATA. ZLRCK is

the Left/Right clock indicating which channel is

currently being received. ZSCLK is the serial bit

clock where ZLRCK and ZSDATA change on the

falling edge and serial data is internally latched on

the rising edge. Note that the serial data starts one

ZSCLK period after ZLRCK transitions. Figure 16

illustrates the clocking on the ZV PORT pins.

10. CONSUMER IEC-958 DIGITAL

INTERFACE (S/PDIF)

The CS4630 supports the industry standard IEC-

958 consumer digital interface. Sometimes this

standard is referred to as S/PDIF, which refers to an

older version of this standard. This output provides

an interface, external to the PC, for storing digital

audio (as in a DAT or recordable CD-ROM) or

playing digital audio from digital speakers.

Figure 17 illustrates the circuit necessary for imple-

mentation of the IEC-958 consumer interface.

An external buffer is required to drive the current

needed for the 75

Ω interface. A current driver is

implemented to increase the transmission range of

the coaxial circuitry.

Figure 18 illustrates an optional fiber optic circuit.

The optical circuit connects directly to the CS4630

and no additional current driver is needed.

ZLRCK

ZSCLK

Left Channel

Right Channel

ZSDATA

6 54 3 210

98 7

15 14 13 12 11 10

654 32 10

9 87

15 14 13 12 11 10

Figure 16. ZV Port Clocking Format

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