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CS4630 数据表(PDF) 10 Page - Cirrus Logic

部件名 CS4630
功能描述  CrystalClear SoundFusion PCI Audio Accelerator
PDF  38 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS4630 数据表(HTML) 10 Page - Cirrus Logic

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CS4630
10
DS445PP1
INDEPENDENT TIMING ENVIRONMENT (T
A = 0 to 70° C; PCIVDD = CRYVDD = 3.3 V; CVDD =
2.5V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0V, Logic 1 = 3.3 V;
Timing reference levels = 1.4 V; XTALI = 12.288 MHz; unless otherwise noted)
Parameter
Symbol
Min
Typ
Max
Units
SCLK output cycle time
tsclk
312
326
-
ns
FSYNC output cycle time (@SCLK falling edge)
tfsync
20000
20833
-
ns
SCLK falling to FSYNC transition
tpd7
-45
2
45
ns
LRCLK output cycle time (@ SCLK rising edge)
tlrclk
20000
20833
-
ns
SCLK rising to LRCLK transition
tpd8
-45
2
45
ns
SCLK falling to SDOUT/SDO2/SDO3 valid
tpd9
-
2
45
ns
SDIN/SDIN2 valid to SCLK rising (SI1F2-0: 010, SI2F1-0: 00)
ts6
30
-
-
ns
SDIN/SDIN2 hold after SCLK rising
(SI1F2-0: 010, SI2F1-0: 00)
th6
30
-
-
ns
SDIN/SDIN2 valid to SCLK falling
(SI1F2-0: 011, SI2F1-0: 01)
ts7
30
-
-
ns
SDIN/SDIN2 hold after SCLK falling
(SI1F2-0: 011, SI2F1-0: 01)
th7
30
-
-
ns
XTAL frequency
12.287
12.288
12.289
MHz
XTALI high time
(Note 4)
35
-
-
ns
XTALI low time
(Note 4)
35
-
-
ns
MCLK output frequency
(Note 4)
12.287
12.288
12.289
MHz
SCLK
FSYNC
LRCLK
SDOUT/SD02/SD03
SDIN/SDIN2
SDIN/SDIN2
tsclk
tpd7
t fsync
tlrclk
tpd9
t pd8
15
0
15
0
ts6
17
16
0
17
16
0
19
18
0
19
18
0
th6
th7
ts7
Figure 5. Independent Timing Configuration



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