数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CS4630 数据表(PDF) 17 Page - Cirrus Logic

部件名 CS4630
功能描述  CrystalClear SoundFusion PCI Audio Accelerator
PDF  38 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS4630 数据表(HTML) 17 Page - Cirrus Logic

Back Button CS4630 Datasheet HTML 13Page - Cirrus Logic CS4630 Datasheet HTML 14Page - Cirrus Logic CS4630 Datasheet HTML 15Page - Cirrus Logic CS4630 Datasheet HTML 16Page - Cirrus Logic CS4630 Datasheet HTML 17Page - Cirrus Logic CS4630 Datasheet HTML 18Page - Cirrus Logic CS4630 Datasheet HTML 19Page - Cirrus Logic CS4630 Datasheet HTML 20Page - Cirrus Logic CS4630 Datasheet HTML 21Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 17 / 38 page
background image
CS4630
DS445PP1
17
4.2
Configuration Space
The content and format of the PCI Configuration Space is given in Table 2.
Byte 3
Byte 2
Byte 1
Byte 0
Offset
Device ID: R/O, 6003h
Vendor ID: R/O, 1013h
00h
Status Register, bits 15-0:
Bit 15 Detected Parity Error: Error Bit
Bit 14 Signalled SERR: Error Bit
Bit 13 Received Master Abort: Error Bit
Bit 12 Received Target Abort: Error Bit
Bit 11 Signalled Target Abort: Error Bit
Bit 10-9 DEVSEL Timing: R/O, 10b (slow)
Bit 8 Data Parity Error Detected: Error Bit
Bit 7 Fast Back to Back Capable: R/O 0
Bit 6 User Definable Features: R/O 0
Bit 5 66MHz Bus: R/O 0
Bit 4 New Capabilities: R/O 1
Bit 3-0Reserved: R/O 0000
Reset Status State: 0410h
Write of 1 to any error bit position clears it.
Command Register, bits 15-0:
Bit 15-10: Reserved, R/O 0
Bit 9 Fast B2B Enable: R/O 0
Bit 8 SERR Enable: R/W, default 0
Bit 7 Wait Control: R/O 0
Bit 6 Parity Error Response: R/W, default 0
Bit 5 VGA Palette Snoop: R/O 0
Bit 4 MWI Enable: R/O 0
Bit 3 Special Cycles: R/O 0
Bit 2 Bus Master Enable: R/W, default 0
Bit 1 Memory Space Enable: R/W, default 0
Bit 0 IO Space Enable: R/O 0
04h
Class Code: R/O 040100h
Class 04h (multimedia device), Sub-class 01h (audio), Interface 00h
Revision ID: R/O 01h
08h
BIST: R/O 0
Header Type:
Bit 7: R/O 0
Bit 6-0: R/O 0 (type 0)
Latency Timer:
Bit 7-3: R/W,default 0
Bit 2-0: R/O 0
Cache Line Size:
R/O 0
0Ch
Base Address Register 0
Device Control Register space, memory mapped. 4 kByte size
Bit 31-12: R/W, default 0. Compare address for register space accesses
Bit 11 - 4: R/O 0, specifies 4 kByte size
Bit 3: R/O 0, Not Prefetchable (Cacheable)
Bit 2-1: R/O 00, Location Type - Anywhere in 32 bit address space
Bit 0: R/O 0, Memory space indicator
10h
Base Address Register 1
Device Memory Array mapped into host system memory space, 1 MByte size
Bit 31-20: R/W, default 0. Compare address for memory array accesses
Bit 19 - 4: R/O 0, specifies 1 MByte size
Bit 3: R/O 0, Not Prefetchable (Cacheable)
Bit 2-1: R/O 00, Location Type - Anywhere in 32 bit address space
Bit 0: R/O 0, Memory space indicator
14h
Base Address Register 2: R/O 00000000h, Unused
18h
Base Address Register 3: R/O 00000000h, Unused
1Ch
Base Address Register 4: R/O 00000000h, Unused
20h
Base Address Register 5: R/O 00000000h, Unused
24h
Cardbus CIS Pointer: R/O 00000000h, Unused
28h
Table 2. PCI Configuration Space



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com