CS4630

34

DS445PP1

JBB2/MCLK - Joystick B Button 2 / Master Clock, I/O

This dual function pin defaults as JBB2 (button 2 input for joystick B). In non-AC ’97 system

configurations, this pin can function as a master (256x sample rate) output clock if enabled.

This pin can also be used as a general purpose polled input if alternate data output streams are

not required.

MIDIIN - MIDI Data Input

This is the serial input pin for the internal MIDI port.

MIDIOUT - MIDI Data Output

This is the serial output pin for the internal MIDI port.

CVDD[3:0] - Core Power Supply

Core/Stream Processor power pins. These pins must be connected to a nominal +2.5 Volts.

CGND[3:0] - Core Ground Supply

Core/Stream Processor ground reference pins.

NC - No Connect

Do not connect any signal to this pin.

12.5 Serial Codec Interface

ABITCLK/SCLK - Primary AC ‘97 Bit Clock / Serial Audio Data Clock, I/O

Master timing clock for serial audio data. In AC ’97 configurations, this pin is an input which

drives the timing for the AC ’97 interface, along with providing the source clock for the

ASYNC/FSYNC - Primary AC ‘97 Frame Sync / Serial Audio Frame Sync, I/O

Framing clock for serial audio data. In AC ’97 configurations, this pin is an output which

indicates the framing for the AC ’97 link. In external DAC configurations, this pin is an

FSYNC output, providing the left/right framing clock.

ASDOUT/SDOUT - Primary AC ‘97 Data Out / Serial Audio Data Out, Output

AC ‘97 serial data out/Serial audio output data.

ARST# - Primary AC ‘97 Reset, Output, Active Low

AC ’97 link reset pin. This pin also functions as a general purpose reset output in non-AC ’97

configurations and will follow RST# to ground, but must be forced high by software.

ASDIN/SDIN - Primary AC ‘97 Data In / Serial Audio Data In, Input, Weak Internal Pulldown

AC ‘97 (2.1) Serial audio input data for the primary AC ‘97 Codec