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CS4630 数据表(PDF) 32 Page - Cirrus Logic |
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CS4630 数据表(HTML) 32 Page - Cirrus Logic |
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32 / 38 page ![]() CS4630 32 DS445PP1 VAUX_SEL - Select 3.3 Vaux, Output, Active High This pin is used to switch the on-card power MOSFET’s to support 3.3 Vaux supply when implementing PME# generation from D3cold power management state. PCIVDD_SENSE - Sense Main System 3.3 V, Input, Active High, Weak Internal Pulldown This pin is used to determine the presence of the main 3.3 V supply. This signal is used in implementing PME# generation from D3cold power management state. If not used, leave un- connected. VAUX_SENSE - Sense 3.3 Vaux, Input, Active High, Weak Internal Pulldown This pin is used to determine the presence of the auxiliary 3.3 Vaux supply. This signal is used in implementing PME# generation from D3cold power management state. If not used, leave un- connected. 12.3 External Interface Pins TEST - Test Mode Strap, Input, Active High This pin is sampled at reset for test mode entry. If it is high at reset, test mode is enabled. This pin must be pulled to ground for normal operation. EEDAT/PCGNT# - EEPROM Data Line / PC/PCI Grant, I/O For add-in card designs, this is the data line for external serial EEPROM containing device configuration data. When used with an external EEPROM (EEPDIS must be low), a 4.7 k Ω pullup resistor is required. In motherboard designs using PC/PCI, this pin is the PC/PCI serialized grant input. In designs with neither of the above requirements, this pin can be used as a general purpose input or open drain output (GPIO2). EECLK/PCREQ# - EEPROM Clock Line / PC/PCI Request, Output For add-in card designs, this is the clock line for external serial EEPROM containing device configuration data (EEPDIS must be low). In motherboard designs using PC/PCI, this pin is the PC/PCI serialized request output. In designs with neither of the above requirements, this pin can be used as a general purpose output pin (GPOUT). EEPDIS - EEPROM Disable, Input, Active High This strapping pin, when tied high, disables the EEPROM interface. When low, the CS4630 checks at power-up for an external EEPROM on the EECLK and EEDAT pins. SDIN2/GPIO - Serial Data Input 2 / General Purpose I/O Pin, I/O This dual function pin defaults as a general purpose I/O pin. In non-AC ’97 system configurations, this pin can function as a second stereo digital data input pin if enabled. |
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