CS4630 datasheet(36/38 Pages) CIRRUS

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CS4630

DS445PP1

12.8 Asynchronous Serial Interface and Enhanced General Purpose I/O

ASCLK/EGPIO[3] - Async. Serial Port Clock / Enhanced Gen. Purpose I/O, I/O

Serial Clock that controls the asynchronous serial interface. As ASCLK, this pin can be either

an asynchronous input bit clock or, when the AC ‘97 interface is enabled, can be an output

programmed for a frequency of ABITCLK/4. When not used as an asynchronous port bit clock,

this pin is enhanced general purpose I/O bit 3 (see EGPIO[7, 2:0] for more details).

ASFCLK/EGPIO[4] - Async. Serial Frame Clock / Enhanced Gen. Purpose I/O, I/O

Serial Frame signal that delineates left from right data. As ASFLCK, this pin can be either an

input L/R framing clock that must be synchronous to ASCLK, or when the AC ‘97 interface is

enabled, an output fixed at ASCLK/64. When not used as an asynchronous port framing signal,

this pin is enhanced general purpose I/O bit 4 (see EGPIO[7, 2:0] for more details).

ASDI/EGPIO[5] - Async. Serial Port Data In / Enhanced Gen. Purpose I/O, I/O

When used as ASDI, stereo data is clocked with ASCLK with ASFCLK delineating left from

right. Otherwise, this pin is enhanced general purpose I/O bit 5 (see EGPIO[7, 2:0] for more

details).

ASDO/EGPIO[6] - Async. Serial Port Data Out / Enhanced Gen. Purpose I/O, I/O

When used as ASDO, stereo data is clocked using ASCLK with ASFCLK delineating left from

right. Otherwise, this pin is enhanced general purpose I/O bit 6 (see EGPIO[7, 2:0] for more

details).

EGPIO[7, 2:0] - Extended General Purpose I/O Bits, I/O

These bits along with bits EGPIO[6:3] have extended programmability and can be used for any

application such as modem DAA control. Programmability features include: direction, polarity,

level/edge and sensitive.

CS4630 数据表(PDF) 36 Page - Cirrus Logic