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SAP5SD-B-G1-R 数据表(PDF) 30 Page - List of Unclassifed Manufacturers |
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SAP5SD-B-G1-R 数据表(HTML) 30 Page - List of Unclassifed Manufacturers |
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30 / 63 page ![]() SAP5S / SAP51 Universal Actuator-Sensor Interface IC Data Sheet July 17, 2012 © 2012 Zentrum Mikroelektronik Dresden AG — Rev. 3.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to changes without notice. 30 of 62 4.3. DC Characteristics – Digital Inputs The following pins contain digital high voltage input stages: - Input-only pin: PFAULT - I/O pins: P1, P3, D1, D3, DSTBn, PSTBn 1, LED1 1 - 3-level I/O pins: P0, P2, D0, D2 3 Table 16: DC Characteristics of digital high voltage input pins Symbol Parameter Min Max Unit Note VOFL Voltage range for input ”offset_low” level 0 1.0 V 3,4 VOFH Voltage range for input ”offset_high” level 1.6 VUOUT V 3,4 VIL2 Voltage range for input ”low” level 0 2.5 V 4 VIH Voltage range for input ”high” level 3.5 VUOUT V IIL Current range for input ”low” level -12 -3 µA VIN = 1V 2 IIH Current range for input ”high” level -10 10 µA V0 VU5R CDL Capacitance at pin DSTBn 10 pF 5 1 PSTBn and LED1 are inputs for test purposes only. 2 The pull-up current is driven by a current source connected to U5R. It stays almost constant for input voltages ranging from 0 to 3.8V. 3 Pins P0, P2, D0 and D2 are used as 3-level inputs - i.e. inputs with offset detection - in Safety Mode only, configuration beyond depends on the slave profile (refer to Table 26 on page 40) 4 The 3-level input pads contain independent comparators for the detection of regular input data level and offset. Refer to Figure 12 on page 50 for constraints to the externally applied voltages in Safety Mode. 5 The internal pull-up current is sufficient to avoid accidental triggering of an IC reset if the DSTBn pin remains unconnected. For external loads at DSTBn a sufficient pull up resistor is required to ensure VIH 3.5V in less than 90ms after the beginning of a DSTBn = Low pulse. 4.4. DC Characteristics – Digital Outputs The following pins contain digital high voltage open drain output stages: - Output-only pin: LED2 - I/O pins: D0 … D3, P0 … P3, DSTBn, PSTBn 1, LED11 Table 17: DC Characteristics of digital high voltage output pins Symbol Parameter Min Max. Unit Note VOL1 Voltage range for output ”low” level 0 1 V IOL1 = 10mA VOL2 Voltage range for output ”low” level 0 0.4 V IOL2 = 2mA IOH Output leakage current -10 10 µA V0H VU5R 1 PSTBn and LED1 are inputs for test purposes only. A slew rate limitation is provided to each digital high voltage output driver which limits the rise and fall times for both High/Low and Low/High transitions to 40…50ns. NOTE: The rise time for a Low/High transition is mainly influenced by the external pull-up resistor. |
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